Clock Control; Fig. 41 Clock Control Circuit Structure - Renesas 4513 User Manual

CLOCK CONTROL

The clock control circuit consists of the following circuits.
• System clock generating circuit
• Control circuit to stop the clock oscillation
Oscillation
X
IN
X circuit
OUT
POF instruction R
S
Note: The wait time control circuit is used to generate the time required to stabilize the f(X

Fig. 41 Clock control circuit structure

Table 23 Clock control register MR
Clock control register MR
MR System clock selection bit
3
Not used
MR
2
MR Not used
1
Not used
MR
0
Note : "R" represents read enabled, and "W" represents write enabled.
MR
3
Division circuit
1
(divided by 2)
0
Q
4513/4514 Group User's Manual
FUNCTION BLOCK OPERATIONS
• Control circuit to switch the middle-speed mode and high-speed
mode
• Control circuit to return from the RAM back-up state
Internal clock
generation circuit
(divided by 3)
RESET
Key-on wake up control register
K0
Falling detected
I1
2
"L" level
0
1
"H" level
I2
2
"L" level
0
1
"H" level
at reset : 1000
2
0 f(X ) (high-speed mode)
IN
1 f(X )/2 (middle-speed mode)
IN
0
This bit has no function, but read/write is enabled.
1
0
This bit has no function, but read/write is enabled.
1
0
This bit has no function, but read/write is enabled.
1
HARDWARE
System clock
Instruction clock
Counter
Wait time (Note)
Software
control circuit
start signal
,K0 ,K0 ,K0
0 1 2 3
Ports P0 , P0
0
Multi-
Ports P0 , P0
2
plexer Ports P1 , P1
0
Ports P1 , P1
2
P3 /INT
0 0
P3 /INT
1 1
IN
at RAM back-up : 1000
2
1
3
1
3
) oscillation.
R/W
1-57