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3.3 List of precautions
Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 F) between pins V
and V
at the shortest distance,
SS
• equalize its wiring in width and length, and
• use relatively thick wire.
In the One Time PROM version, CNV
pin. Accordingly, when using this pin, connect this pin to V
through a resistor about 5 k
Prescaler
Stop the prescaler operation to change its frequency dividing ra-
tio.
Timer count source
Stop timer 1, 2, 3, or 4 counting to change its count source.
Reading the count value
Stop timer 1, 2, 3, or 4 counting and then execute the TAB1,
TAB2, TAB3, or TAB4 instruction to read its data.
Writing to reload registers R1 and R3
When writing data to reload registers R1 or R3 while timer 1 or
timer 3 is operating, avoid a timing when timer 1 or timer 3
underflows.
P3
/INT0 pin
0
When the interrupt valid waveform of the P3
changed with the bit 2 of register I1 in software, be careful about
the following notes.
• Clear the bit 0 of register V1 to "0" before the interrupt valid wave-
form of P3
/INT0 pin is changed with the bit 2 of register I1 (refer
0
to Figure 44 ).
• Depending on the input state of the P3
interrupt request flag (EXF0) may be set when the interrupt valid
waveform is changed. Accordingly, clear bit 2 of register I1, and
execute the SNZ0 instruction to clear the EXF0 flag after execut-
ing at least one instruction (refer to Figure 44 )
. . .
LA
4
; (
TV1A
; The SNZ0 instruction is valid ...........
LA
4
;
TI1A
; Interrupt valid waveform is changed
NOP
...........................................................
SNZ0
; The SNZ0 instruction is executed
NOP
. . .
: this bit is not related to the setting of INT0 pin.
Fig. 44 External 0 interrupt program example
pin is also used as V
SS
in series at the shortest distance.
/INT0 pin is
0
/INT0 pin, the external 0
0
0
)
2
4513/4514 Group User's Manual
P3
/INT1 pin
1
When the interrupt valid waveform of P3
with the bit 2 of register I2 in software, be careful about the fol-
DD
lowing notes.
• Clear the bit 1 of register V1 to "0" before the interrupt valid wave-
form of P3
/INT1 pin is changed with the bit 2 of register I2 (refer
1
to Figure 45 ).
PP
• Depending on the input state of the P3
interrupt request flag (EXF1) may be set when the interrupt valid
SS
waveform is changed. Accordingly, clear bit 2 of register I2 and
execute the SNZ1 instruction to clear the EXF1 flag after execut-
ing at least one instruction (refer to Figure 45 ).
. . .
LA
8
; (
TV1A
; The SNZ1 instruction is valid ...........
LA
8
TI2A
; Change of the interrupt valid waveform
NOP
...........................................................
SNZ1
; The SNZ1 instruction is executed
NOP
. . .
: this bit is not related to the setting of INT1.
Fig. 45 External 1 interrupt program example
One Time PROM version
The operating power voltage of the One Time PROM version is
2.5 V to 5.5 V.
Multifunction
The input of D
, D
, P2
6
7
CMP0+, CMP1-, CMP1+, and I/O of P4
when CNTR0, CNTR1, S
and A
–A
are selected.
IN4
IN7
APPENDIX
3.3 List of precautions
/INT1 pin is changed
1
/INT1 pin, the external 1
1
0
)
2
–P2
, I/O of P3
and P3
, input of CMP0-,
0
2
0
1
–P4
can be used even
0
3
, S
, S
, INT0, INT1, A
CK
OUT
IN
–A
IN0
IN3
3-21
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