Fig. 2.3.5 Cntr1 Input Setting Example - Renesas 4513 User Manual

4500 series 4-bit single-chip microcomputer
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APPLICATION
2.3 Timers
Disable Interrupts
Timer 2 interrupt is temporarily disabled.
Interrupt enable flag INTE
Interrupt control register V1
Stop Timer Operation
Timer 1 operation is temporarily stopped.
Timer 2 count source is selected.
Timer control register W2
Set Timer Value
Timer 2 count time is set.
Timer 2 reload register R2 "63
Clear Interrupt Request
Timer 2 interrupt activated condition is cleared.
Timer 2 interrupt request flag T2F "0"
Note when the interrupt request is cleared
When
interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
Start Timer 2 Operation
Timer 2 temporarily stopped is restarted.
Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled.
Interrupt control register V1
Interrupt enable flag INTE
" ": it can be "0" or "1."

Fig. 2.3.5 CNTR1 input setting example

However, specify the pulse width input to CNTR0 pin/CNTR1 pin. Refer to section "2.3.4 Notes on use" for
the timer external input period condition.
2-34
"0"
b3
0
is executed, considering the skip of the next instruction according to the
Timer control register W2
b3
1
"1"
4513/4514 Group User's Manual
All interrupts disabled (DI instruction)
b0
Timer 2 interrupt occurrence disabled
(TV1A instruction)
b3
b0
Timer 2 stop (TW2A instruction)
0
1
0
CNTR0 input selected for count source
"
16
Timer count value 99 set (T2AB instruction)
Timer 2 interrupt activated condition cleared
g 0 h
(SNZT2 instruction)
b3
b0
Timer 2 operation start (TW2A instruction)
1
1
0
b0
Timer 2 interrupt occurrence enabled
(TV1A instruction)
All interrupts enabled (EI instruction)

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