Fig. 34 Power-On Reset Circuit Example; Fig. 35 Internal State At Reset; Table 19 Port State At Reset - Renesas 4513 User Manual

HARDWARE
FUNCTION BLOCK OPERATIONS
(1) Power-on reset
Reset can be performed automatically at power on (power-on re-
set) by connecting resistors, a diode, and a capacitor to RESET
pin. Connect RESET pin and the external circuit at the shortest dis-
tance.
V
D D
RESET pin
(Note)
Note:
This symbol represents a parasitic diode.
Applied potential to RESET pin must be V

Fig. 34 Power-on reset circuit example

(2) Internal state at reset
Table 19 shows port state at reset, and Figure 35 shows internal
state at reset (they are the same after system is released from re-
set). The contents of timers, registers, flags and RAM except
shown in Figure 35 are undefined, so set the initial value to them.

Table 19 Port state at reset

Name
D –D
0 5
D /CNTR0, D /CNTR1
6 7
P0 –P0
0 3
P1 –P1
0 3
P2 /S , P2 /S , P2 /S
0 CK 1 OUT 2
P3 /INT0, P3 /INT1
0 1
P3 , P3 (Note 4)
2 3
P4 /A –P4 /A (Note 4)
0 IN4 3 IN7
P5 –P5 (Note 4)
0 3
Notes 1: Output latch is set to "1."
2: Pull-up transistor is turned OFF.
3: After system is released from reset, port P5 is in the input mode. (Direction register FR0 = 0000
4: The 4513 Group does not have these ports.
1-50
Internal reset signal
Voltage drop detection circuit
WEF
Function
D –D
0 5
D , D
6 7
P0 –P0
0 3
P1 –P1
0 3
P2 –P2
IN
0 2
P3 , P3
0 1
P3 , P3
2 3
P4 P4
0– 3
P5 –P5
0 3
4513/4514 Group User's Manual
Watchdog timer output
Power-on
or less.
DD
High impedance (Note)
High impedance (Notes 1, 2)
High impedance
High impedance (Note 1)
High impedance (Note 1)
High impedance (Note 3)
V
DD
RESET pin voltage
Reset state
Internal reset signal
Reset released
State
)
2