Notes On Use; Table 2.9.7 Interrupt Control Register I2 - Renesas 4513 User Manual

APPLICATION
2.9 RAM back-up
(4) Interrupt control register I2
The interrupt valid waveform for INT1 pin/return level selection bit is assigned to bit 2, the INT1 pin
edge detection circuit control bit is assigned to bit 1, and the INT1 pin timer 1 control enable bit is
assigned to bit 1.
Set the contents of this register through register A with the TI2A instruction.
In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A.
Table 2.9.7 shows the interrupt control register I2.

Table 2.9.7 Interrupt control register I2

Interrupt control register I2
I2 Not used
3
Interrupt valid waveform for INT1
I2 pin/return level selection bit
2
(Note 2)
INT1 pin edge detection circuit
I2
1
control bit
INT1 pin
I2
0
timer 3 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled.
2: When the contents of I2
Accordingly, clear EXF1 flag with the SNZ1 instruction.

2.9.3 Notes on use

(1) Key-on wakeup function
After setting ports (P1 specified with register PU0 and P0) which key-on wakeup function is valid to
"H," execute the POF instruction.
"L" level is input to the falling edge detection circuit even if one of ports which key-on wakeup
function is valid is in the "L" level state, and the edge is not detected.
(2) POF instruction
Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM
back-up state.
Note that system cannot enter the RAM back-up state when executing only the POF instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
(3) Return from RAM back-up
After system returns from RAM back-up, set the undefined registers and flags.
Especially, be sure to set data pointer (registers Z, X, Y).
2-62
at reset : 0000
0
This bit has no function, but read/write is enabled.
1
Falling waveform ("L" level of INT1 pin is recognized
0
with the SNZI1 instruction)/"L" level
Rising waveform ("H" level of INT1 pin is recognized
1
with the SNZI1 instruction)/"H" level
One-sided edge detected
0
Both edges detected
1
Disabled
0
Enabled
1
is changed, the external interrupt request flag EXF1 may be set.
2
4513/4514 Group User's Manual
at RAM back-up : state retained
2
R/W