Table 2.1.4 Direction Register Fr0; Table 2.1.5 Timer Control Register W6 - Renesas 4513 User Manual

APPLICATION
2.1 I/O pins
(4) Direction register FR0 (The 4513 Group does not have this register.)
Register FR0 is used to switch to input/output of P5
Set the contents of this register through register A with the TFR0A instruction.
Table 2.1.4 shows the direction register FR0.

Table 2.1.4 Direction register FR0

Direction register FR0 (Note 2)
FR0
Port P5 input/output control bit
3
3
FR0 Port P5 input/output control bit
2 2
FR0
Port P5 input/output control bit
1
1
FR0 Port P5 input/output control bit
0 0
Notes 1: "W" represents write enabled.
2: The 4513 Group does not have register FR0.
(5) Timer control register W6
D /CNTR0 function selection bit is assigned to bit 0, D
6
bit 2.
Set the contents of this register through register A with the TW6A instruction.
The contents of register W6 is transferred to register A with the TAW6 instruction.
Table 2.1.5 shows the timer control register W6.

Table 2.1.5 Timer control register W6

Timer control register W6
W6 CNTR1 output control bit
3
W6
D /CNTR1 function selection bit
2
7
W6 CNTR0 output control bit
1
W6 D /CNTR0 function selection bit
0 6
Notes 1: "R" represents read enabled, and "W" represents write enabled.
2: When setting ports, W6
2-6
at reset : 0000
0 Port P5
3
1
Port P5
3
0
Port P5
2
1 Port P5
2
0 Port P5
1
1
Port P5
1
0
Port P5
0
1
Port P5
0
at reset : 0000
0
Timer 3 underflow signal output divided by 2
1 CNTR1 output control by timer 4 underflow signal divided by 2
0
D (I/O)/CNTR1 input
7
1
CNTR1 I/O/D
0
Timer 1 underflow signal output divided by 2
1
CNTR0 output control by timer 2 underflow signal divided by 2
0 D (I/O)/CNTR0 input
6
1
CNTR0 I/O/D
and W6 are not used.
3 1
4513/4514 Group User's Manual
–P5 .
0 3
at RAM back-up : state retained
2
input
output
input
output
input
output
input
output
/CNTR1 function selection bit is assigned to
7
at RAM back-up : state retained
2
(input)
7
(input)
6
W
R/W