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Renesas 4513 User Manual

Renesas 4513 User Manual

4500 series 4-bit single-chip microcomputer
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Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003

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  • Page 1 Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.
  • Page 2 MITSUBISHI 4-BIT SINGLE-CHIP MICROCOMPUTER 4500 SERIES 4513/4514 Group User’s Manual...
  • Page 3 keep safety first in your circuit designs ! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
  • Page 4 4-bit microcomputer. After reading this manual, the user should have a through knowledge of the functions and features of the 4513/4514 Group and should be able to fully utilize the product. The manual starts with specifications and ends with application examples.

  • Page 5: Appendix

    Be sure to refer to this chapter because this chapter also includes necessary information for systems development. Note: In this manual, the 4514 Group is mainly described. The differences from the 4513 Group are described at the related points.

  • Page 6: Table Of Contents

    ROM ORDERING METHOD ... 1-58 LIST OF PRECAUTIONS ... 1-59 SYMBOL ... 1-62 LIST OF INSTRUCTION FUNCTION ... 1-63 INSTRUCTION CODE TABLE... 1-66 MACHINE INSTRUCTIONS ... 1-70 CONTROL REGISTERS ... 1-84 BUILT-IN PROM VERSION ... 1-88 4513/4514 Group User’s Manual Table of contents...
  • Page 7 2.9.1 RAM back-up mode ... 2-59 2.9.2 Related register ... 2-60 2.9.3 Notes on use ... 2-62 2.10 Oscillation circuit ... 2-63 2.10.1 Oscillation circuit ... 2-63 2.10.2 Oscillation operation ... 2-64 2.10.3 Notes on use ... 2-64 4513/4514 Group User’s Manual Table of contents...
  • Page 8 3.4.6 Providing of watchdog timer function by software ... 3-28 3.5 Mask ROM order confirmation form ... 3-30 3.6 Mark specification form ... 3-36 3.7 Package outline ... 3-39 –A line and V 4513/4514 Group User’s Manual Table of contents IN7 ... line ... 3-26 3-17...
  • Page 9 List of figures CHAPTER 1 HARDWARE PIN CONFIGURATION (TOP VIEW) 4513 Group ... 1-4 PIN CONFIGURATION (TOP VIEW) 4514 Group ... 1-5 BLOCK DIAGRAM (4513 Group) ... 1-6 BLOCK DIAGRAM (4514 Group) ... 1-7 PORT BLOCK DIAGRAMS ... 1-12 External interrupt circuit structure ... 1-16 Fig.
  • Page 10 Fig. 47 Analog input external circuit example-1 ... 1-60 Fig. 48 Analog input external circuit example-2 ... 1-60 Fig. 49 Pin configuration of built-in PROM version of 4513 Group... 1-88 Fig. 50 Pin configuration of built-in PROM version of 4514 Group... 1-88 Fig.
  • Page 11 Fig. 3.4.11 Watchdog timer by software ... 3-29 pin ... 3-25 pin of the One Time PROM version ... 3-26 line and the V pattern on the underside of an oscillator ... 3-28 4513/4514 Group User’s Manual line ... 3-26...
  • Page 12 Table 2.3.5 Timer control register W3 ... 2-29 Table 2.3.6 Timer control register W4 ... 2-29 Table 2.4.1 Serial I/O mode register J1 ... 2-41 Table 2.4.2 Recommended operating conditions (serial I/O) ... 2-48 List of tables 4513/4514 Group User’s Manual...
  • Page 13 Table 3.1.5 A-D converter recommended operating conditions... 3-6 Table 3.1.6 A-D converter characteristics ... 3-6 Table 3.1.7 Voltage drop detection circuit characteristics... 3-6 Table 3.1.8 Voltage comparator recommended operating conditions ... 3-7 Table 3.1.9 Voltage comparator characteristics ... 3-7 viii 4513/4514 Group User’s Manual...

  • Page 14: Chapter 1 Hardware

    C H A P T E R C H A P T E R 1 HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS SYMBOL LIST OF INSTRUCTION FUNCTION INSTRUCTION CODE TABLE MACHINE INSTRUCTIONS CONTROL REGISTERS...
  • Page 15 HARDWARE 4513/4514 Group User’s Manual...
  • Page 16 DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION DESCRIPTION The 4513/4514 Group is a 4-bit single-chip microcomputer de- signed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial I/O, four 8-bit timers (each timer has a reload register), and 10-bit A-D conver ter.

  • Page 17: Chapter 1 Hardware

    HARDWARE PIN CONFIGURATION PIN CONFIGURATION (TOP VIEW) 4513 Group /CNTR0 /CNTR1 RESET Outline 32P4B M34513Mx-XXXFP /CNTR /CNTR M34513ExFP Outline 32P6B-A 4513/4514 Group User’s Manual /CMP1+ /CMP1- /CMP0+ /CMP0- /INT1 /INT0 VDCE /CMP1+ /CMP1- /CMP0+ /CMP0- /INT1...

  • Page 18: Pin Configuration (Top View) 4514 Group

    PIN CONFIGURATION (TOP VIEW) 4514 Group /CNTR0 /CNTR1 RESET Outline 42P2R-A 4513/4514 Group User’s Manual HARDWARE PIN CONFIGURATION /CMP1+ /CMP1- /CMP0+ /CMP0- /INT1 /INT0 VDCE...
  • Page 19 HARDWARE BLOCK DIAGRAM BLOCK DIAGRAM (4513 Group) 4513/4514 Group User’s Manual...
  • Page 20 HARDWARE BLOCK DIAGRAM BLOCK DIAGRAM (4514 Group) 4513/4514 Group User’s Manual...
  • Page 21 INT1, respectively. The 4513 Group does not have ports P3 4-bit I/O port; The 4513 Group does not have this port. 4-bit I/O port with a direction register; The 4513 Group does not have this port. 1-bit I/O; CNTR0 pin is also used as port D 1-bit I/O;...
  • Page 22 Input spectively. 4-bit I/O port (2-bit I/O port for the 4513 Group). For input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. Ports P3 are also used as INT0 and INT1, respectively.

  • Page 23: Multifunction

    , P2 –P2 , CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P3 , INT0, INT1, and A 3: The 4513 Group does not have P4 CONNECTIONS OF UNUSED PINS Open (when using an external clock). Connect to V VDCE Connect to V –D...

  • Page 24: Port Function

    –P4 Port P5 –P5 (Note 2) Notes 1: The 4513 Group does not have P3 2: The 4513 Group does not have these ports. DEFINITION OF CLOCK AND CYCLE System clock The system clock is the basic clock for controlling this product.

  • Page 25: Port Block Diagrams

    OP1A instruction 1-12 Pull-up transistor IAP0 instruction Pull-up transistor IAP0 instruction Pull-up transistor IAP1 instruction Pull-up transistor IAP1 instruction This symbol represents a parasitic diode on the port. • i represents 0, 1, 2, or 3. • 4513/4514 Group User’s Manual...

  • Page 26: Port Block Diagrams

    Synchronous clock output for serial transfer Key-on wakeup input • • Applied potential to ports P2 • i represents 0, 1, 2, or 3. • The 4513 Group does not have ports P3 IAP2 instruction Register A IAP2 instruction Register A...
  • Page 27 Decoder CMP1 Decoder IAP4 instruction Decoder • • i represents 0, 1, 2, or 3. • The 4513 Group does not have port P4. 4513/4514 Group User’s Manual /CMP0- /CMP0+ /CMP1- /CMP1+ –P4 This symbol represents a parasitic diode on the port.
  • Page 28 This symbol represents a parasitic diode on the port. • • Applied potential to ports D • i represents 0, 1, 2, or 3. • The 4513 Group does not have port P5. 4513/4514 Group User’s Manual HARDWARE PIN DESCRIPTION –P5...

  • Page 29: External Interrupt Circuit Structure

    Rising detection circuit Wakeup Skip SNZI0 One-sided edge Falling detection circuit Both edges Rising detection circuit Wakeup Skip SNZI1 This symbol represents a parasitic diode on the port. 4513/4514 Group User’s Manual External 0 EXF0 interrupt External 1 EXF1 interrupt...

  • Page 30: Function Block Operations

    Fig. 2 RAR instruction execution example Register E Fig. 3 Registers A, B and register E Specifying address The contents of The contents of register D register A 4513/4514 Group User’s Manual HARDWARE FUNCTION BLOCK OPERATIONS <Carry> (CY) (M(DP)) Addition <Result>...

  • Page 31: Fig. 5 Stack Registers (Sks) Structure

    Returning to the BM instruction execution Note : address with the RT instruction, and the BM instruction becomes the NOP instruction. Fig. 6 Example of operation at subroutine call 4513/4514 Group User’s Manual Executing RT instruction (SP) = 0 (SP) = 1...

  • Page 32: Fig. 7 Program Counter (Pc) Structure

    SD, RD, or SZD instruction (Figure 9). (bits 6 to 0) which speci- Fig. 7 Program counter (PC) structure Fig. 8 Data pointer (DP) structure Fig. 9 SD instruction execution example 4513/4514 Group User’s Manual HARDWARE FUNCTION BLOCK OPERATIONS Program counter Specifying page...

  • Page 33: Program Memoy (Rom)

    0082 0084 0086 0088 008A 008C 008E 00FF Fig. 11 Page 1 (addresses 0080 4513/4514 Group User’s Manual 8 7 6 5 4 3 2 1 Page 0 Interrupt address page Page 1 Subroutine special page Page 2 Page 3...

  • Page 34: Data Memory (Ram)

    M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 4 bits (1536 bits) Register Z Register X 128 words 4513/4514 Group User’s Manual HARDWARE FUNCTION BLOCK OPERATIONS RAM size 128 words 4 bits (512 bits) 256 words 4 bits (1024 bits) 384 words 4 bits (1536 bits)

  • Page 35: Interrupt Function

    Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt A-D interrupt Serial I/O interrupt Table 5 Interrupt enable bit function Interrupt enable bit 4513/4514 Group User’s Manual Interrupt Activated condition address Level change of Address 0 INT0 pin in page 1...

  • Page 36: Fig. 13 Program Example Of Interrupt Processing

    • Completion of • A-D conversion Completion of serial I/O transfer Activated condition Fig. 15 Interrupt system diagram 4513/4514 Group User’s Manual HARDWARE FUNCTION BLOCK OPERATIONS The address of main routine to be executed when returning EXF0 EXF1 INTE SIOF...

  • Page 37: Table 6 Interrupt Control Registers

    Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) 4513/4514 Group User’s Manual at RAM back-up : 0000 at RAM back-up : 0000 at RAM back-up : 0000...

  • Page 38: Fig. 16 Interrupt Sequence

    Serial I/O interrupts Notes 1: The 4513/4514 Group operates in the middle-speed mode after system is released from reset. 2: The address is stacked to the last cycle. 3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.

  • Page 39: External Interrupts

    HARDWARE FUNCTION BLOCK OPERATIONS EXTERNAL INTERRUPTS The 4513/4514 Group has two external interrupts (external 0 and external 1). An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupts can be controlled with the interrupt control registers I1 and I2.
  • Page 40 Set both the external 1 interrupt enable bit (V1 flag to “1.” The external 1 interrupt is now enabled. Now when a valid wave- form is input to the P3 external 1 interrupt occurs. 4513/4514 Group User’s Manual HARDWARE FUNCTION BLOCK OPERATIONS /INT1 pin. function. However, the /INT1 pin.

  • Page 41: Table 8 External Interrupt Control Registers

    Falling waveform (“L” level of INT1 pin is recognized with the SNZI1 instruction)/“L” level Rising waveform (“H” level of INT1 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled 4513/4514 Group User’s Manual...

  • Page 42: Timers

    TIMERS The 4513/4514 Group has the programmable timers. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt re- quest flag is set to “1,”...

  • Page 43: Table 9 Function Related Timers

    HARDWARE FUNCTION BLOCK OPERATIONS The 4513/4514 Group timer consists of the following circuits. • Prescaler : frequency divider • Timer 1 : 8-bit programmable timer • Timer 2 : 8-bit programmable timer • Timer 3 : 8-bit programmable timer • Timer 4 : 8-bit programmable timer (Timers 1 to 4 have the interrupt function, respectively) •...

  • Page 44: Fig. 19 Timers Structure

    Register B Register A 16-bit timer (WDT) Instruction clock 1 - - - - - - - - - - - 15 16 WRST instruction Reset signal 4513/4514 Group User’s Manual HARDWARE FUNCTION BLOCK OPERATIONS ORCLK Timer 1 interrupt T1AB...
  • Page 45 Timer 1 underflow signal output divided by 2 CNTR0 output control by timer 2 underflow signal divided by 2 (I/O)/CNTR0 input CNTR0 (I/O)/D (input) 4513/4514 Group User’s Manual at RAM back-up : 0000 at RAM back-up : 0000 Count source Count source...

  • Page 46: Table 10 Timer Control Registers

    Data can be read from timer 2 with the TAB2 instruction. When reading the data, stop the counter and then execute the TAB2 in- struction. The output from D signal divided by 2 can be controlled. 4513/4514 Group User’s Manual HARDWARE /CNTR0 pin by timer 2 underflow 1-33...
  • Page 47 P3 and P3 /INT1 pin. Once set, the count start synchronous circuit is cleared by clearing the bit I1 4513/4514 Group User’s Manual /CNTR0, D /CNTR1) /CNTR1 pin function can be...

  • Page 48: Watchdog Timer

    FFFF 0000 WDF1 flag WDF2 flag WRST instruction executed Fig. 21 Program example to enter the RAM back-up mode 4513/4514 Group User’s Manual HARDWARE FUNCTION BLOCK OPERATIONS BFFF 3FFF WRST System reset instruction executed •...

  • Page 49: Serial I/O

    HARDWARE FUNCTION BLOCK OPERATIONS SERIAL I/O The 4513/4514 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data. Serial I/O consists of; • serial I/O register SI • serial I/O mode register J1 • serial I/O transmission/reception completion flag (SIOF) •...

  • Page 50: Fig. 23 Serial I/O Register State When Transferring

    Register J1 controls the synchronous clock, P2 and P2 register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A. 4513/4514 Group User’s Manual HARDWARE FUNCTION BLOCK OPERATIONS Serial I/O register (SI) pin function.

  • Page 51: Fig. 24 Serial I/O Connection Example

    Table 13 shows the data transfer sequence. Slave (external clock) signal (Bit 3) OUT, (Bit 3) 4513/4514 Group User’s Manual (Bit 0) Serial I/O mode register J1 External clock selected as a synchronous clock Serial I/O port...

  • Page 52: Fig. 25 Timing Of Serial I/O Data Transfer

    Rising of SCK : serial input Fig. 25 Timing of serial I/O data transfer ’ ’ –S : the contents of slave serial I/O register Falling of SCK : serial output 4513/4514 Group User’s Manual HARDWARE FUNCTION BLOCK OPERATIONS 1-39...

  • Page 53: Table 13 Processing Sequence Of Data Transfer From Master To Slave

    SST instruction • “L” level (reception possible) is output from port D RD instruction [Reception] • Check reception completes. SNZSI instruction • “H” level is output from port D SD instruction [Data processing] 4513/4514 Group User’s Manual ) and outputting...

  • Page 54: A-D Converter

    A-D CONVERTER The 4513/4514 Group has a built-in A-D conversion circuit that performs conversion by 10-bit successive comparison method. Table 14 shows the characteristics of this A-D converter. This A- D converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset val- ues.

  • Page 55: Table 15 A-D Control Registers

    A-D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD. (5) A-D control register Q1 Register Q1 is used to select one of analog input pins. The 4513 Group does not have A pins with register Q1.

  • Page 56: Table 16 Change Of Successive Comparison Register Ad During A-D Conversion

    9: 9th comparison result A: 10th comparison result The 4513/4514 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A-D conversion stops after 62 machine cycles (46.5 s when f(X 4.0 MHz in high-speed mode) from the start, and the conversion re-...

  • Page 57: Fig. 27 A-D Conversion Timing Chart

    M(Z, X, Y) = (0, 0, 0). 1-44 62 machine cycles (Bit 3) (Bit 3) Set an arbitrary value Fig. 28 Setting registers 4513/4514 Group User’s Manual (Bit 0) A-D control register Q2 function selected A-D conversion mode (Bit 0) A-D control register Q1...

  • Page 58: Fig. 29 Comparator Operation Timing Chart

    AD is transferred to the high-order 2 bits of register A, si- multaneously, the low-order 2 bits of register A is “0.” 8 machine cycles Comparator operation completed. (The value of ADF is determined) 4513/4514 Group User’s Manual HARDWARE –P4 are set to pins for analog input, –P4 I/O.

  • Page 59: Fig. 30 Definition Of A-D Conversion Accuracy

    Full-scale transition voltage (V b–a [LSB] [LSB] Actual A-D conversion characteristics –V Ideal line of A-D conversion between V –V 1022 4513/4514 Group User’s Manual and V of actual A-D conversion characteristics. 1022 Analog voltage and V and V by 1...

  • Page 60: Voltage Comparator

    VOLTAGE COMPARATOR The 4513/4514 Group has 2 voltage comparator circuits that perform comparison of voltage between 2 pins. Table 17 shows the characteristics of this voltage comparison. CMP0–/A – CMP0 CMP0+/A – CMP1–/A CMP1 CMP1+/A Note: Bits 0 and 1 of register Q3 can be only read.

  • Page 61: Table 18 Voltage Comparator Control Register Q3

    • Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 passed from the voltage comparator function becomes valid. 4513/4514 Group User’s Manual s) is...

  • Page 62: Reset Function

    16895 times. is counted 16892 to 16895 times. Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. 4513/4514 Group User’s Manual HARDWARE Software starts (address 0 in page 0) Software starts...

  • Page 63: Fig. 34 Power-On Reset Circuit Example

    Notes 1: Output latch is set to “1.” 2: Pull-up transistor is turned OFF. 3: After system is released from reset, port P5 is in the input mode. (Direction register FR0 = 0000 4: The 4513 Group does not have these ports. 1-50 Internal reset signal...
  • Page 64 • Register X ... • Register Y ... • Register Z ... • Stack pointer (SP) ... Fig. 35 Internal state at reset FUNCTION BLOCK OPERATIONS 4513/4514 Group User’s Manual HARDWARE (Interrupt disabled) (Interrupt disabled) (Interrupt disabled) (Prescaler and timer 1 stopped)

  • Page 65: Voltage Drop Detection Circuit

    V Fig. 37 Voltage drop detection circuit operation waveform 1-52 Voltage drop detection circuit Watchdog timer output (detection voltage). 4513/4514 Group User’s Manual Internal reset signal The microcomputer starts operation after f(X ) is counted 16892 to 16895 times.

  • Page 66: Ram Back-Up Mode

    RAM BACK-UP MODE The 4513/4514 Group has the RAM back-up mode. When the EPOF and POF instructions are executed continuously, system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not ex- ecuted before the POF instruction.

  • Page 67: Table 21 Return Source And Return Condition

    RAM back-up state. Select the return level (“L” level or “H” level) with the bit 2 of register I2 ac- cording to the external state before going into the RAM back-up state. 4513/4514 Group User’s Manual Remarks...

  • Page 68: Fig. 38 State Transition

    ) oscillation Return input (Stabilizing time a ) ) oscillation is automatically generated by hardware. Fig. 40 Start condition identified example using the SNZP in- struction 4513/4514 Group User’s Manual HARDWARE FUNCTION BLOCK OPERATIONS ) stop (RAM back-up mode) Software start P = “1”...

  • Page 69: Table 22 Key-On Wakeup Control Register, Pull-Up Control Register, And Interrupt Control

    Falling waveform (“L” level of INT1 pin is recognized with the SNZI1 instruction)/“L” level Rising waveform (“H” level of INT1 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled 4513/4514 Group User’s Manual...

  • Page 70: Clock Control

    )/2 (middle-speed mode) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. 4513/4514 Group User’s Manual HARDWARE System clock Instruction clock Counter...

  • Page 71: Rom Ordering Method

    = 4.0 V to 5.5 V = 2.5 V to 5.5 V 4513/4514 Group User’s Manual 4513/4514 N o t e : E x t e r n a l l y c o n n e c t a...

  • Page 72: List Of Precautions

    CMP0+, CMP1-, CMP1+, and I/O of P4 when CNTR0, CNTR1, S and A /INT0 pin, the external 0 4513/4514 Group User’s Manual HARDWARE LIST OF PRECAUTIONS /INT1 pin is changed /INT1 pin is changed with the bit 2 of register I2 (refer /INT1 pin, the external 1 ;...

  • Page 73: Fig. 46 A-D Converter Operating Mode Program Example

    Program counter Make sure that the PC the built-in ROM. Port P3 In the 4513 Group, when the IAP3 instruction is executed, note that the high-order 2 bits of register A is undefined. 4513/4514 Group User’s Manual About 1k –P4 are set to pins for analog input, –P4...
  • Page 74 Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 s) is passed from the voltage comparator function become valid. 4513/4514 Group User’s Manual HARDWARE LIST OF PRECAUTIONS 1-61...

  • Page 75: Symbol

    Timer 4 Note : The 4513/4514 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accord- ingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.

  • Page 76: List Of Instruction Function

    Carry (A) + n n = 0 to 15 (A) AND (M(DP)) (A) OR (M(DP)) (CY) (CY) (CY) = 0 ? 4513/4514 Group User’s Manual HARDWARE LIST OF INSTRUCTION FUNCTION Group- Mnemonic Function SB j (Mj(DP)) j = 0 to 3...
  • Page 77 TAI2 (I2) TI2A (I2) TAW1 (W1) TW1A (W1) TAW2 (W2) TW2A (W2) TAW3 (W3) TW3A (W3) *: The 4513 Group does not have these instructions. 1-64 Group- Mnemonic Function TAW4 (W4) TW4A (W4) TAW6 (W6) TW6A (W6) TAB1 –T1 –T1 T1AB –R1...
  • Page 78 (J1) TJ1A (J1) (SIOF) Serial I/O starting SNZSI (SIOF) = 1 ? After skipping (SIOF) *: The 4513 Group does not have these instructions. LIST OF INSTRUCTION FUNCTION Group- Mnemonic Function TABAD –AD –AD However, in the com- parator mode, –AD...

  • Page 79: Instruction Code Table

    HARDWARE INSTRUCTION CODE TABLE INSTRUCTION CODE TABLE (for 4513 Group) –D 000000 000001 000010 000011 Hex. –D notation 0000 BMLA 0001 – – 0010 – – 0011 SNZP – 0100 – SEAn 0101 – SEAM 0110 – – – 0111 –...
  • Page 80 INSTRUCTION CODE TABLE (continued) (for 4513 Group) –D 100000 100001 100010 100011 Hex. –D notation – TW3A OP0A T1AB 0000 – TW4A OP1A T2AB 0001 TJ1A – – T3AB 0010 – TW6A OP3A T4AB 0011 TQ1A – – – 0100 TQ2A –...
  • Page 81 TABP EPOF TABP TABP TABP TABP TABP TABP TABP TABP –D show the high-order 6 bits of the machine language code. The hexadecimal representa- 4513/4514 Group User’s Manual 001100 001010 001011 001101 001110 001111 TABP TABP TABP TABP TABP TABP...
  • Page 82 – – – – – – – – – ADST –D show the high-order 6 bits of the machine language code. The hexadecimal 4513/4514 Group User’s Manual HARDWARE INSTRUCTION CODE TABLE 101100 101010 101011 101101 101110 101111 XAMI XAMD WRST...

  • Page 83: Machine Instructions

    3 x y 0 4 8 0 1 3 0 1 7 2 C j 2 D j 2 F j 2 E j 2 B j 4513/4514 Group User’s Manual Function –E –E –E –E –DR –A –A –DR –A...
  • Page 84 After transferring the contents of register A to M(DP), an exclusive OR operation is performed between reg- ister X and the value j in the immediate field, and stores the result in register X. Datailed description 4513/4514 Group User’s Manual HARDWARE MACHINE INSTRUCTIONS...
  • Page 85 0 1 C 0 1 D 0 5 C 0 4 C 0 2 j 0 2 6 0 2 5 0 7 n 4513/4514 Group User’s Manual Function n = 0 to 15 (SP) (SP) + 1 (SK(SP)) (PC) –DR –A...
  • Page 86 – Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Datailed description specified by registers A and D in page p. 4513/4514 Group User’s Manual HARDWARE MACHINE INSTRUCTIONS 1-73...
  • Page 87 0 3 0 2 p p 0 4 6 0 4 4 0 4 5 0 0 4 0 0 5 0 3 8 0 3 9 4513/4514 Group User’s Manual Function –a –a (Note) –DR –A (Note) (SP) (SP) + 1...
  • Page 88 (EXF1) = 1 Skips the next instruction when the contents of EXF1 flag is “1.” After skipping, clears (0) to the EXF1 flag. Datailed description 4513/4514 Group User’s Manual HARDWARE MACHINE INSTRUCTIONS specified by registers D and A in specified by registers D...
  • Page 89 2 1 0 2 4 E 2 1 1 2 5 0 2 1 3 4513/4514 Group User’s Manual Function = 1 : (INT0) = “H” ? = 0 : (INT0) = “L” ? = 1 : (INT1) = “H” ? = 0 : (INT1) = “L”...
  • Page 90 ) of register I2 is “1” : Skips the next instruction when the level of INT1 pin is “H.” ) of register I2 is “0” : Skips the next instruction when the level of INT1 pin is “L.” 4513/4514 Group User’s Manual HARDWARE...
  • Page 91 2 3 2 2 7 3 2 3 3 2 3 F 2 3 B 2 8 0 2 8 1 2 8 2 2 8 3 4513/4514 Group User’s Manual Function –T1 –T1 –R1 –T1 –R1 –T1 –T2 –T2 –R2...
  • Page 92 After skipping, clears (0) to T3F flag. (T4F) = 1 – Skips the next instruction when the contents of T4F flag is “1.” After skipping, clears (0) to T4F flag. Datailed description 4513/4514 Group User’s Manual HARDWARE MACHINE INSTRUCTIONS 1-79...
  • Page 93 OP3A IAP4* OP4A* IAP5* OP5A* TK0A TAK0 TPU0A TAPU0 TFR0A* *: The 4513 Group does not have these instructions. 1-80 Instruction code Hexadecimal notation 2 6 0 2 2 0 2 6 1 2 2 1 2 6 2 2 6 3...
  • Page 94 Transfers the contents of register A to pull-up control register PU0. – – Transfers the contents of pull-up control register PU0 to register A. – – Transfers the contents of register A to direction register FR0. Datailed description 4513/4514 Group User’s Manual HARDWARE MACHINE INSTRUCTIONS 1-81...
  • Page 95 0 0 0 0 0 2 0 5 B 0 0 3 2 A 0 2 5 2 2 1 6 2 4 6 2 0 6 4513/4514 Group User’s Manual Function –SI –SI –SI –SI (J1) (J1) (SIOF) Serial I/O starting...
  • Page 96 Transfers the contents of the high-order 2 bits of register A to the high-order 2 bits of voltage comparator control register Q3, and the comparison result of the voltage comparator is transferred to the low-order 2 bits of the register Q3. Datailed description 4513/4514 Group User’s Manual HARDWARE MACHINE INSTRUCTIONS 1-83...

  • Page 97: Control Registers

    Rising waveform (“H” level of INT1 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled 4513/4514 Group User’s Manual at RAM back-up : 0000 at RAM back-up : 0000 at RAM back-up : 0000...
  • Page 98 Timer 1 underflow signal output divided by 2 CNTR0 output control by timer 2 underflow signal divided by 2 (I/O)/CNTR0 input CNTR0 (I/O)/D (input) 4513/4514 Group User’s Manual HARDWARE CONTROL REGISTERS at RAM back-up : 0000 at RAM back-up : 0000...

  • Page 99: Table 23 Clock Control Register Mr

    A-D control register Q2 A-D operation mode selection bit and P4 pin function selec- tion bit (Not used for the 4513 Group) pin function selection bit (Not used for the 4513 Group) pin function selection bit (Not used for the 4513 Group)
  • Page 100 Port P5 input/output control bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: The 4513 Group does not have the direction register FR0. at reset : 0000 at RAM back-up : state retained Key-on wakeup not used...

  • Page 101: Built-In Prom Version

    HARDWARE BUILT-IN PROM VERSION BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4513/4514 Group has programmable ROM version software compatible with mask ROM. The built-in PROM of One Time PROM version can be written to and not be erased.

  • Page 102: Fig. 51 Prom Memory Map

    Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 °C exceeding 100 hours. Fig. 52 Flow of writing and test of the product shipped in blank 4513/4514 Group User’s Manual HARDWARE BUILT-IN PROM VERSIONS Programming adapter PCA7442SP...
  • Page 103 HARDWARE BUILT-IN PROM VERSION 1-90 4513/4514 Group User’s Manual...

  • Page 104: Chapter 2 Application

    C H A P T E R 2 C H A P T E R APPLICATION 2.1 I/O pins 2.2 Interrupts 2.3 Timers 2.4 Serial I/O 2.5 A-D converter 2.6 Voltage comparator 2.7 Reset 2.8 Voltage drop detection circuit 2.9 RAM back-up 2.10 Oscillation circuit...

  • Page 105: I/O Ports

    APPLICATION 2.1 I/O pins 2.1 I/O pins The 4513/4514 Group has the twenty-eight I/O pins (eighteen I/O pins for 4513 Group), three input pins. (Ports P2 –P2 , P3 , P3 CNTR0 and CNTR1 pins, respectively). This section describes each port I/O function, related registers, application example using each port function and notes.
  • Page 106 (4) Port P3 Port P3 is a 4-bit I/O port for the 4514 Group, and a 2-bit I/O port for the 4513 Group. Input/output of port P3 Data input to port P3 Set the output latch of specified port P3i (i=0 to 3) to “1” with the OP3A instruction. If the output latch is set to “0,”...

  • Page 107: Related Registers

    Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON 4513/4514 Group User’s Manual –D ” or more to register Y. is also used as CNTR1. Accordingly, when ) and bit 2 (W6 ) of timer control register and P1 –P1...

  • Page 108: Table 2.1.2 Key-On Wakeup Control Register K0

    –A with register Q1 after setting register Q2. 3: For the 4513 Group, these bits are not used. 4: For the 4513 Group, only read/write of these bits is enabled. 5: When setting ports, Q2 at reset : 0000 at RAM back-up : state retained...

  • Page 109: Table 2.1.4 Direction Register Fr0

    APPLICATION 2.1 I/O pins (4) Direction register FR0 (The 4513 Group does not have this register.) Register FR0 is used to switch to input/output of P5 Set the contents of this register through register A with the TFR0A instruction. Table 2.1.4 shows the direction register FR0.

  • Page 110: Port Application Examples

    Figure 2.1.1 shows the key input and Figure 2.1.2 shows the key input timing. M34513/M34514 Fig. 2.1.1 Key input by key scan SW12 SW11 SW16 SW15 4513/4514 Group User’s Manual APPLICATION SW10 SW14 2.1 I/O pins SW13...

  • Page 111: Fig. 2.1.2 Key Scan Input Timing

    Fig. 2.1.2 Key scan input timing Switching key input selection port (D Stabilizing wait time for input Reading port (key input) Key input period IAP0 IAP0 Input to Input to SW5–SW8 SW9–SW12 4513/4514 Group User’s Manual IAP0 IAP0 Input to Input to SW13–SW16 SW1–SW4...

  • Page 112: Notes On Use

    “1.” Also, for the port input, the port input function of the pin functions as analog input is undefined. (7) Notes on port P3 In the 4513 Group, when the IAP3 instruction is executed, the contents of high-order 2 bits of register A are undefined.

  • Page 113: Table 2.1.6 Connections Of Unused Pins

    V , turn off their pull-up transistors (register while the key-on wakeup functions are left valid, the system fails or V or V at the shortest distance using a thick wire. 4513/4514 Group User’s Manual through a resistor or...

  • Page 114: Interrupts

    2.2 Interrupts The 4513/4514 Group has eight interrupt sources : external (INT0, INT1), timer 1, timer 2, timer 3, timer 4, A-D, and serial I/O. This section describes individual types of interrupts, related registers, application examples using interrupts and notes.
  • Page 115 A in page 1. When the interrupt is not used The interrupt is disabled and the SNZT4 instruction is valid when the bit 1 of register V2 is set to “0.” 2-12 4513/4514 Group User’s Manual...

  • Page 116: Related Registers

    When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. Note: The interrupt enabled with the EI instruction is performed after the EI instruction and one more instruction. 4513/4514 Group User’s Manual APPLICATION 2.2 Interrupts 2-13...

  • Page 117: Table 2.2.1 Interrupt Control Register V1

    Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) 4513/4514 Group User’s Manual...

  • Page 118: Table 2.2.3 Interrupt Control Register I1

    Rising waveform (“H” level of INT1 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled is changed, the external interrupt request flag EXF1 may be set. 4513/4514 Group User’s Manual APPLICATION 2.2 Interrupts 2-15...

  • Page 119: Interrupt Application Examples

    3 interrupt occurs every 1 ms. Figure 2.2.7 shows a setting example of the timer 3 constant period interrupt. 2-16 “H”). “H”). 4513/4514 Group User’s Manual “L” or “L” or ) = 4.0 MHz, and the ) = 4.0 MHz, and the...

  • Page 120: Fig. 2.2.1 Int0 Interrupt Operation Example

    /INT0 “L” Fig. 2.2.1 INT0 interrupt operation example An interrupt occurs after the valid waveform “falling” is detected. An interrupt occurs after the valid waveform “rising” is detected. 4513/4514 Group User’s Manual APPLICATION 2.2 Interrupts ) = 4.0 MHz, 2-17...

  • Page 121: Fig. 2.2.2 Int0 Interrupt Setting Example

    Set to input (OP3A instruction) Both edges detection selected (TI1A instruction) INT0 interrupt activated condition cleared (SNZ0 instruction) INT0 interrupt occurrence enabled (TV1A instruction) All interrupts enabled (EI instruction) “1” INT0 interrupt execution started 4513/4514 Group User’s Manual...

  • Page 122: Fig. 2.2.3 Int1 Interrupt Operation Example

    APPLICATION 2.2 Interrupts “H” /INT1 “L” “H” An interrupt occurs after the valid waveform “falling” is detected. /INT1 An interrupt occurs after the valid waveform “rising” is detected. “L” Fig. 2.2.3 INT1 interrupt operation example 4513/4514 Group User’s Manual 2-19...

  • Page 123: Fig. 2.2.4 Int1 Interrupt Setting Example

    Set to input (OP3A instruction) Both edges detection selected (TI2A instruction) INT1 interrupt activated condition cleared (SNZ1 instruction) INT1 interrupt occurrence enabled (TV1A instruction) All interrupts enabled (EI instruction) “1” INT1 interrupt execution started 4513/4514 Group User’s Manual...

  • Page 124: Fig. 2.2.5 Timer 1 Constant Period Interrupt Setting Example

    Timer 1 operation start (TW1A instruction) Prescaler operation stop Timer 1 interrupt occurrence enabled (TV1A instruction) All interrupts enabled (EI instruction) “1” Constant period interrupt execution start (82+1) Prescaler Timer 1 clock dividing count ratio value 4513/4514 Group User’s Manual APPLICATION 2.2 Interrupts 2-21...

  • Page 125: Fig. 2.2.6 Timer 2 Constant Period Interrupt Setting Example

    (SNZT2 instruction) Timer 2 operation start (TW2A instruction) Timer 2 interrupt occurrence enabled (TV1A instruction) “1” All interrupts enabled (EI instruction) Constant period interrupt execution start (39+1) 16-bit Timer 2 clock fixed count dividing value frequency 4513/4514 Group User’s Manual...

  • Page 126: Fig. 2.2.7 Timer 3 Constant Period Interrupt Setting Example

    Timer 3 operation start (TW3A instruction) Prescaler operation start (TW1A instruction) Timer 3 interrupt occurrence enabled (TV2A instruction) All interrupts enabled (EI instruction) “1” Constant period interrupt execution start (82+1) Prescaler Timer 3 dividing count ratio value 4513/4514 Group User’s Manual APPLICATION 2.2 Interrupts 2-23...

  • Page 127: Fig. 2.2.8 Timer 4 Constant Period Interrupt Setting Example

    Prescaler operation start (TW1A instruction) Timer 4 interrupt occurrence enabled (TV2A instruction) “1” All interrupts enabled (EI instruction) Constant period interrupt execution start –1 (82+1) (249+1) Prescaler Timer 3 Timer 4 clock dividing count count ratio value value 4513/4514 Group User’s Manual A below.)

  • Page 128: Notes On Use

    I2, and execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction. (3) Multiple interrupts Multiple interrupts cannot be used in the 4513/4514 Group. (4) Notes on interrupt processing When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to “0” (interrupt disable state).

  • Page 129: Timers

    2.3 Timers 2.3 Timers The 4513/4514 Group has four 8-bit timers (each has a reload register) and a 16-bit fixed dividing frequency timer which has the watchdog timer function. This section describes individual types of timers, related registers, application examples using timers and notes.

  • Page 130: Related Registers

    Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) and V2 are not used. 4513/4514 Group User’s Manual APPLICATION 2.3 Timers at RAM back-up : 0000 at RAM back-up : 0000...

  • Page 131: Table 2.3.3 Timer Control Register W1

    : 0000 at RAM back-up : state retained Stop (state retained) Operating This bit has no function, but read/write is enabled. Timer 1 underflow signal Prescaler output CNTR0 input 16-bit timer (WDT) underflow signal 4513/4514 Group User’s Manual Count source...

  • Page 132: Table 2.3.5 Timer Control Register W3

    RAM back-up : state retained Stop (state retained) Operating This bit has no function, but read/write is enabled. Timer 3 underflow signal Prescaler output CNTR1 input Not available 4513/4514 Group User’s Manual APPLICATION 2.3 Timers Count source Count source 2-29...

  • Page 133: Timer Application Examples

    Specifications: The low-frequency pulse from external as the timer 2 count source is input to CNTR0 pin, and the timer 2 interrupt request occurs every 100 counts. Figure 2.3.5 shows the setting example of CNTR0 input. 2-30 4513/4514 4513/4514 Group User’s Manual ) = 4.0 MHz, and the CNTR0...

  • Page 134: Fig. 2.3.2 Watchdog Timer Function

    Watchdog timer provides a method to reset the system when a program run-away occurs. In the 4513/4514 Group, bit 15 of 16-bit timer is counted twice for the watchdog timer. Accordingly, when the watchdog timer function is set to be valid, execute the WRST instruction at a certain period which consists of timer 16-bit timers’...

  • Page 135: Fig. 2.3.3 Constant Period Measurement Setting Example

    Timer 1 operation start (TW1A instruction) Prescaler operation start Timer 1 interrupt occurrence enabled (TV1A instruction) “1” All interrupts enabled (EI instruction) Constant period interrupt execution start –1 (249+1) Prescaler Timer 1 clock dividing count ratio value 4513/4514 Group User’s Manual...

  • Page 136: Fig. 2.3.4 Cntr0 Output Setting Example

    Timer 1 operation start (TW1A instruction) Prescaler operation start Timer 1 interrupt occurrence enabled (TV1A instruction) “1” All interrupts enabled (EI instruction) CNTR0 input pin set (TW6A instruction) is set to “1.” 4513/4514 Group User’s Manual APPLICATION 2.3 Timers (SD instruction) 2-33...

  • Page 137: Fig. 2.3.5 Cntr1 Input Setting Example

    Timer count value 99 set (T2AB instruction) Timer 2 interrupt activated condition cleared g 0 h (SNZT2 instruction) Timer 2 operation start (TW2A instruction) Timer 2 interrupt occurrence enabled (TV1A instruction) “1” All interrupts enabled (EI instruction) 4513/4514 Group User’s Manual...

  • Page 138: Fig. 2.3.6 Cntr0 Output Control Setting Example

    Timer count value 41 set (T3AB instruction) “FF ” Timer count value 255 set (T4AB instruction) Timer 3 operation start (TW3A instruction) Timer 4 operation start (TW4A instruction) All interrupts enabled (EI instruction) “1” 4513/4514 Group User’s Manual APPLICATION 2.3 Timers 2-35...

  • Page 139: Fig. 2.3.7 Timer Start By External Input Setting Example (1)

    0 h Timer 1 interrupt activated condition cleared “0” (SNZT1 instruction) INT0 interrupt activated condition cleared “0” (SNZ0 instruction) Timer 1 interrupt occurrence enabled (TV1A instruction) “1” All interrupts enabled (EI instruction) Timer start by external input 4513/4514 Group User’s Manual...

  • Page 140: Fig. 2.3.8 Timer Start By External Input Setting Example (2)

    Fig. 2.3.8 Timer start by external input setting example (2) Interrupt control register I1 Timer count value 82 set (T1AB instruction) “52 ” Interrupt control register I1 4513/4514 Group User’s Manual APPLICATION 2.3 Timers (TI1A instruction) 1 0 0 (TI1A instruction)

  • Page 141: Fig. 2.3.9 Watchdog Timer Setting Example

    Watchdog timer enable flag WEF set (WRST instruction) Watchdog timer flag WDF1 cleared “0” g0 h (WRST instruction) Main routine execution Repeat • • • • • • ; WDF flag cleared ; POF instruction enabled 4513/4514 Group User’s Manual...

  • Page 142: Notes On Use

    (4) Writing to reload registers R1, R3 When writing data to reload registers R1, R3 while timer 1 and 3 are operating, avoid a timing when timers 1 and 3 underflow. 4513/4514 Group User’s Manual APPLICATION 2.3 Timers 2-39...

  • Page 143: Serial I/O

    APPLICATION 2.4 Serial I/O 2.4 Serial I/O The 4513/4514 Group has a clock-synchronous serial I/O which can be used to transmit and receive 8-bit data. This section describes serial I/O functions, related registers, application examples using serial I/O and notes.

  • Page 144: Related Registers

    Instruction clock signal divided by 4 Input ports P2 , P2 Serial I/O ports S External clock Internal clock (instruction clock divided by 4 or 8) 4513/4514 Group User’s Manual APPLICATION 2.4 Serial I/O , P2 selected /input ports P2...

  • Page 145: Operation Description

    Note: The control signal is used to inform the master by the pin level that the slave is in a ready state to receive. The 4513/4514 Group does not have a control pin exclusively used for serial I/O. Accordingly, if a control signal is required, use the normal input/output ports.

  • Page 146: Fig. 2.4.4 Serial I/O Transfer Timing

    : the contents of slave serial I/O register Rising of S : serial input Falling of S : serial output ’–M ’: previous MSB contents of master and slave Fig. 2.4.4 Serial I/O transfer timing ’ ’ 4513/4514 Group User’s Manual APPLICATION 2.4 Serial I/O 2-43...
  • Page 147 “H” after a transmit operation is started first. 2-44 pin synchronously with the falling edges of the shift pin synchronously with the rising edges of the shift through to transmit or receive multiple data in succession. 4513/4514 Group User’s Manual...

  • Page 148: Serial I/O Application Example

    2.4.4 Serial I/O application example (1) Serial I/O Outline: The 4513/4514 Group can communicate with peripheral ICs. Specifications: Figure 2.4.2 Serial I/O connection example. Figure 2.4.5 shows the master serial I/O setting example, and Figure 2.4.6 shows the slave serial I/O setting example.

  • Page 149: Fig. 2.4.5 Master Serial I/O Setting Example

    Execute Receive Data Data received by serial transfer is executed. Register SI register A, register B (TABSI instruction) When serial communication is executed, 4513/4514 Group User’s Manual When interrupt is used Serial I/O interrupt occurrence enabled (TV2A instruction) All interrupts enabled “1”...

  • Page 150: Fig. 2.4.6 Slave Serial I/O Example

    Serial I/O interrupt temporarily disabled is enabled. Interrupt control register V2 Interrupt enable flag INTE pin initial level = “H” level register A, register B (TABSI instruction) 4513/4514 Group User’s Manual APPLICATION 2.4 Serial I/O When interrupt is used Serial I/O interrupt occurrence...

  • Page 151: Notes On Use

    = 2.0 V to 5.5 V (Note 2) = 4.0 V to 5.5 V High-speed mode = 2.5 V to 5.5 V = 2.0 V to 5.5 V (Note 2) “L” pulse width “H” pulse width 4513/4514 Group User’s Manual Limits Unit Min. Typ. Max.

  • Page 152: A-D Converter

    2.5 A-D converter The 4513/4514 Group has an A-D converter with the 10-bit successive comparison method: 4 channels for the 4513 Group, 8 channels for the 4514 Group. This A-D converter can also be used as a comparator to compare analog voltages input from the analog input pin with preset values.

  • Page 153: Related Registers

    –A with register Q1 after setting register Q2. 3: In the 4513 Group, these bits are not used. 4: In the 4513 Group, only read/write of these bits is enabled. 2-50 at reset : 0000 at power down : state retained This bit has no function, but read/write is enabled.

  • Page 154: A-D Converter Application Examples

    A-D Conversion Interrupt Occur register A and register B (TABAD instruction) high-order 2 bits of register A (TALA instruction) “0” is set to low-order 2 bits of register A 4513/4514 Group User’s Manual APPLICATION 2.5 A-D converter pin for this analog input.

  • Page 155: Notes On Use

    Fig. 2.5.4 Analog input external circuit example-2 • • • Clear bit 2 of register V2 to “0”... performed with the SNZAD instruction • • • 4513/4514 Group User’s Manual About 1 k (Note) Note: i = 0 to 7...

  • Page 156: Table 2.5.3 Recommended Operating Conditions (When Using A-D Converter)

    = 2.7 V to 5.5 V (middle-speed mode) = 4.5 V to 5.5 V (high-speed mode) = 4.0 V to 5.5 V (high-speed mode) = 2.7 V to 5.5 V (middle-speed mode) 4513/4514 Group User’s Manual APPLICATION 2.5 A-D converter Limits Min.

  • Page 157: Voltage Comparator

    APPLICATION 2.6 Voltage comparator 2.6 Voltage comparator The 4513/4514 Group has two voltage comparators; CMP0-, CMP0+, CMP1-, CMP1+. This section describes the voltage comparator function, related registers, and notes. 2.6.1 Voltage comparator function (1) CMP0 Voltage comparison The voltage of CMP0- is compared with that of CMP0+, and the result is stored into bit 0 of the voltage comparator control register Q3.

  • Page 158: Voltage Comparator Function

    Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written. Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 s) is passed from the voltage comparator function become valid. 4513/4514 Group User’s Manual 2-55...

  • Page 159: Reset

    (f(X shows the oscillation stabilizing time. 2.7.1 Reset circuit The 4513/4514 Group has the power-on reset circuit and voltage drop detection circuit. (1) Power-on reset Reset can be performed automatically at power on (power-on reset) by connecting resistors, a diode, and a capacitor to RESET pin.

  • Page 160: Internal State At Reset

    (Interrupt disabled) (Interrupt disabled) (Prescaler, timer 1 stopped) (Timer 2 stopped) (Timer 3 stopped) (Timer 4 stopped) (External clock selected, serial I/O port not selected)) (Port P5 input mode) 4513/4514 Group User’s Manual APPLICATION 2.7 Reset “ ” represents undefined. 2-57...

  • Page 161: Voltage Drop Detection Circuit

    Note: Refer to section “3.1 Electrical characteristics” for the reset voltage of the voltage drop detection circuit. 2-58 Internal reset signal Voltage drop detection circuit Watchdog timer output (detection voltage). 4513/4514 Group User’s Manual The microcomputer starts operation after f(X ) is counted 16892 to 16895 times.

  • Page 162: Ram Back-Up

    16-bit timer (WDT) (Note 3) A-D conversion completion flag (ADF) Serial I/O transmit/receive completion flag (SIOF) O (Note 5) Interrupt enable flag (INTE) 4513/4514 Group User’s Manual APPLICATION 2.9 RAM back-up Function RAM back-up (Note 3) (Note 3) (Note 3)

  • Page 163: Related Register

    Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used 4513/4514 Group User’s Manual Remarks P = “1” Warm start Cold start –P0 , P1 –P1...

  • Page 164: Table 2.9.5 Pull-Up Control Register Pu0

    SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled is changed, the external interrupt request flag EXF0 may be set. 4513/4514 Group User’s Manual APPLICATION 2.9 RAM back-up –P0 , P1 –P1 at RAM back-up : state retained...

  • Page 165: Notes On Use

    SNZI1 instruction)/“L” level Rising waveform (“H” level of INT1 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled is changed, the external interrupt request flag EXF1 may be set. 4513/4514 Group User’s Manual...

  • Page 166: Oscillation Circuit

    2.10 Oscillation circuit The 4513/4514 Group has an internal oscillation circuit to produce the clock required for microcomputer operation. The clock signal f(X ) is obtained by connecting a ceramic resonator to X 2.10.1 Oscillation circuit (1) f(X ) clock generating circuit The clock signal f(X ) is obtained by connecting a ceramic resonator externally.

  • Page 167: Oscillation Operation

    2.10.2 Oscillation operation System clock is supplied to CPU and peripheral device as the standard clock for the microcomputer operation. For the 4513/4514 Group, the clock (f(X circuit is selected with the register MR. Figure 2.10.2 shows the structure of the clock control circuit.

  • Page 168: Chapter 3 Appendix

    C H A P T E R C H A P T E R 3 APPENDIX 3.1 Electrical characteristics 3.2 Typical characteristics 3.3 List of precautions 3.4 Notes on noise 3.5 Mask ROM confirmation form 3.6 Mark specification form 3.7 Package outline...

  • Page 169: Absolute Maximum Ratings

    Tstg Conditions RESET RESET Output transistors in cut-off state Package: 42P2R Ta = 25 °C Package: 32P6B Package: 32P4B 4513/4514 Group User’s Manual Unit Ratings –0.3 to 7.0 –0.3 to V +0.3 –0.3 to 13 –0.3 to V +0.3 –0.3 to V +0.3...

  • Page 170: Table 3.1.2 Recommended Operating Conditions 1

    P0, P1, P4, P5, S (Note) RESET (Note) –D (Note) P0, P1, P4, P5, S (Note) P5, D, RESET P0, P1, P3, P4 4513/4514 Group User’s Manual APPENDIX 3.1 Electrical characteristics Limits Min. Typ. Max. 4.2 MHz 3.0 MHz 4.2 MHz 2.0 MHz 1.5 MHz...

  • Page 171: Electrical Characteristics

    One Time PROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode 4513/4514 Group User’s Manual Limits Typ. Min. = 2.5 V to 5.5 V = 2.0 V to 5.5 V = 2.5 V to 5.5 V = 4.0 V to 5.5 V...
  • Page 172 = 5 V = 3 V = 5 V = 3 V = 5 V = 3 V = 5 V = 3 V 4513/4514 Group User’s Manual APPENDIX 3.1 Electrical characteristics Limits Min. Typ. Max. = –10 mA = –5 mA...

  • Page 173: A-D Converter Recommended Operating Conditions

    Comparator mode = 5.12 V = 3.072 V ) = 4.0 MHz, Middle-speed mode ) = 4.0 MHz, High-speed mode Test conditions Ta = 25 °C = 5.0 V 4513/4514 Group User’s Manual Limits Unit Min. Typ. Max. Limits Unit Min.

  • Page 174: Voltage Comparator Characteristics

    CMP1- > CMP1+, CMP1- < CMP1+ = 5.0 V Machine cycle –D –D –P0 –P1 –P3 –P4 –P5 –P0 –P1 –P2 –P3 –P4 –P5 4513/4514 Group User’s Manual APPENDIX 3.1 Electrical characteristics Limits Min. Typ. Max. 0.3V 0.7V Limits Min. Typ. Max. Mi+1 Unit Unit...

  • Page 175: Typical Characteristics

    (1) CPU operating, middle-speed mode (2) CPU operating, high-speed mode Supply voltage V Supply voltage V 4513/4514 Group User’s Manual ) = 4 MHz ) = 1 MHz ) = 4 MHz ) = 1 MHz Ta = 25 °C...
  • Page 176 A-D operating, middle-speed mode (4) A-D operating, high-speed mode Supply voltage V Supply voltage V 4513/4514 Group User’s Manual APPENDIX 3.2 Typical characteristics Ta = 25 °C ) = 4 MHz ) = 1 MHz Ta = 25 °C ) = 4 MHz...
  • Page 177 APPENDIX 3.2 Typical characteristics (5) RAM back-up 3-10 Supply voltage V 4513/4514 Group User’s Manual Ta = 25 °C...

  • Page 178: Vol -Iol Characteristics

    –I characteristics (1) Ports P0, P1, P4, P5, S (2) Port P3, RESET pin Output voltage V Output voltage V 4513/4514 Group User’s Manual APPENDIX 3.2 Typical characteristics = 6 V = 5 V = 4 V = 3 V = 2 V Ta = 25 °C...
  • Page 179 –D (4) Pins D /CNTR0, D /CNTR1 3-12 Output voltage V Output voltage V 4513/4514 Group User’s Manual Ta = 25 °C = 6 V = 5 V = 4 V = 3 V = 2 V Ta = 25 °C...

  • Page 180: Voh -Ioh Characteristics (Port P5)

    3.2.4 V –R characteristics (Ports P0, P1) = 2 V = 3 V Output voltage V Supply voltage V 4513/4514 Group User’s Manual APPENDIX 3.2 Typical characteristics = 5 V = 6 V = 4 V Ta = 25 °C Ta = 25 °C...

  • Page 181: A-D Converter Typical Characteristics

    “1022” to “1023.” In Figure 3.2.1, this is the value of of actual A-D conversion characteristics. In Figure 3.2.1, this is the value of ERROR in each of 4513/4514 Group User’s Manual +1LSB -1LSB 1022 1023...
  • Page 182 ) = 2 MHz, high-speed mode -1.5 -4.5 -1.5 -4.5 -1.5 -4.5 -1.5 -4.5 1LSB WIDTH ERRO R STEP No. STEP No. STEP No. STEP No. 4513/4514 Group User’s Manual APPENDIX 3.2 Typical characteristics Ta = 25 °C 1008 1024 3-15...
  • Page 183 = 5.12 V, f(X ) = 4 MHz, high-speed mode -2.5 -7.5 -2.5 -7.5 -2.5 -7.5 -2.5 -7.5 3-16 1LSB WIDTH ERRO R STEP No. STEP No. STEP No. STEP No. 4513/4514 Group User’s Manual Ta = 25 °C 1008 1024...

  • Page 184: Analog Input Current Characteristics Pins Ain0 -Ain7

    ) = 2 MHz, middle-speed mode (2) V = 3.0 V, f(X ) = 4 MHz, middle-speed mode -100 –A Analog input voltage V Analog input voltage V 4513/4514 Group User’s Manual APPENDIX 3.2 Typical characteristics Ta = 25 °C Ta = 25 °C 3-17...
  • Page 185 ) = 2 MHz, high-speed mode (4) V = 5.0 V, f(X ) = 4 MHz, high-speed mode -120 -160 -200 3-18 Analog input voltage V Analog input voltage V 4513/4514 Group User’s Manual Ta = 25 °C Ta = 25 °C...

  • Page 186: Vdd -Vih /Vil Characteristics

    (1) RESET pin (2) Ports P0, P1, P2, P3, P4, P5, D, X Supply voltage V pin, VDCE pin Supply voltage V 4513/4514 Group User’s Manual APPENDIX 3.2 Typical characteristics Ta = 25 °C (rating value) (rating value) Ta = 25 °C...

  • Page 187: Detection Voltage Temperature Characteristics Of Voltage Drop Detection Circuit

    3.2 Typical characteristics Pins INT0, INT1, CNTR0, CNTR1, S 3.2.8 Detection voltage temperature characteristics of voltage drop detection circuit 3-20 Supply voltage V Storage temperature range Ta (°C) 4513/4514 Group User’s Manual Ta = 25 °C (rating value) (rating value)

  • Page 188: List Of Precautions

    CMP0+, CMP1-, CMP1+, and I/O of P4 when CNTR0, CNTR1, S /INT0 pin, the external 0 and A 4513/4514 Group User’s Manual APPENDIX 3.3 List of precautions /INT1 pin is changed /INT1 pin is changed with the bit 2 of register I2 (refer /INT1 pin, the external 1 ;...

  • Page 189: Fig. 46 A-D Converter Operating Mode Program Example

    Program counter Make sure that the PC the built-in ROM. Port P3 In the 4513 Group, when the IAP3 instruction is executed, note that the high-order 2 bits of register A is undefined. 4513/4514 Group User’s Manual About 1k –P4 are set to pins for analog input, –P4...
  • Page 190 Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 s) is passed from the voltage comparator function become valid. 4513/4514 Group User’s Manual APPENDIX 3.3 List of precautions 3-23...

  • Page 191: Notes On Noise

    (2) Wiring for RESET input pin Reset circuit Fig. 3.4.2 Wiring for the RESET input pin 4513/4514 Group User’s Manual Make the length of wiring which is connected to the RESET input pin as short as possible. Especially, connect a capacitor across the RESET input pin and the V shortest possible wiring.

  • Page 192: Fig. 3.4.3 Wiring For Clock I/O Pins

    This may cause a microcomputer malfunction or a program runaway. O.K. Fig. 3.4.4 Wiring for CNV level of a level of an 4513/4514 Group User’s Manual APPENDIX 3.4 Notes on noise pin to the V and V Noise O.K.

  • Page 193: Connection Of Bypass Capacitor Across

    APPENDIX 3.4 Notes on noise (5) Wiring to V pin of One Time PROM version In the built-in PROM version of the 4513/4514 Group, the CNV pin is also used as the built-in PROM power supply input pin V When the V...

  • Page 194: Wiring To Analog Input Pins

    Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. 4513/4514 Group User’s Manual APPENDIX 3.4 Notes on noise Reason...

  • Page 195: Setup For I/O Ports

    This example assumes that interrupt processing is repeated multiple times in a single main routine processing. lines 4513/4514 Group User’s Manual or more to an I/O port software...

  • Page 196: Fig. 3.4.11 Watchdog Timer By Software

    0 or less. Interrupt processing routine Main routine (SWDT) (SWDT) Interrupt processing Main processing (SWDT) Interrupt processing Main routine routine errors Fig. 3.4.11 Watchdog timer by software (SWDT)—1 (SWDT) Return errors 4513/4514 Group User’s Manual APPENDIX 3.4 Notes on noise 3-29...

  • Page 197: Mask Rom Order Confirmation Form

    27C256 0000 2.00K 07FF 2.00K 4000 47FF 7FFF of low-order and high-order 5-bit data. 4513/4514 Group User’s Manual Mask ROM number Date: Section head signature R e s p o n s i b l e officer M34513M2-XXXFP (hexadecimal notation)

  • Page 198: Chapter 3 Appendix

    7FFF 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 of low-order and high-order 5-bit data. 4513/4514 Group User’s Manual APPENDIX Mask ROM number...
  • Page 199 7FFF 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 of low-order and high-order 5-bit data. 4513/4514 Group User’s Manual Mask ROM number Date:...
  • Page 200 7FFF 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 of low-order and high-order 5-bit data. 4513/4514 Group User’s Manual APPENDIX Mask ROM number...
  • Page 201 7FFF 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 of low-order and high-order 5-bit data. 4513/4514 Group User’s Manual Mask ROM number Date:...
  • Page 202 7FFF 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 of low-order and high-order 5-bit data. 4513/4514 Group User’s Manual APPENDIX Mask ROM number...
  • Page 203 Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit) 4513/4514 Group User’s Manual (periods), and (commas) are usable. Mitsubishi logo is not required Special logo required...
  • Page 204 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 7 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &, 4513/4514 Group User’s Manual APPENDIX 3.6 Mark specification form (periods), (commas) are usable.
  • Page 205 Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. 4513/4514 Group User’s Manual (periods), (commas) are usable. is not required, check the box below.

  • Page 206: Package Outline

    JEDEC Code LQFP32-P-77-0.80 Weight(g) Lead Material – Alloy 42/Cu Alloy Weight(g) Lead Material – Alloy 42 Detail F 4513/4514 Group User’s Manual APPENDIX 3.7 Package outline Plastic 32pin 400mil SDIP Dimension in Millimeters Symbol – – 0.51 – – 0.35 0.45...
  • Page 207 3.7 Package outline 42P2R-A EIAJ Package Code JEDEC Code SSOP42-P-450-0.80 3-40 Weight(g) Lead Material – 0.63 Alloy 42/Cu Alloy 4513/4514 Group User’s Manual Plastic 42pin 450mil SSOP Recommended Mount Pad Dimension in Millimeters Symbol – – – – – –...
  • Page 208 MITSUBISHI SEMICONDUCTORS USER’S MANUAL 4513/4514 Group Dec. First Edition 1998 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
  • Page 209 REVISION DESCRIPTION LIST 4513/4514 GROUP USER'S MANUAL Rev. Rev. Revision Description date First Edition 981211 (1/1)
  • Page 210 User’s Manual 4513/4514 Group New publication, effective Dec. 1998. © 1998 MITSUBISHI ELECTRIC CORPORATION. Specifications subject to change without notice.

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