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HARDWARE
FUNCTION BLOCK OPERATIONS
Table 15 A-D control registers
A-D control register Q1
Q1
Not used
3
Q1
2
Q1
Analog input pin selection bits (Note 2)
1
Q1
0
A-D control register Q2
Q2
A-D operation mode selection bit
3
P4
/A
and P4
3
IN7
Q2
2
tion bit (Not used for the 4513 Group)
P4
/A
pin function selection bit
1
IN5
Q2
1
(Not used for the 4513 Group)
P4
/A
pin function selection bit
0
IN4
Q2
0
(Not used for the 4513 Group)
Notes 1: "R" represents read enabled, and "W" represents write enabled.
2: Select A
–A
with register Q1 after setting register Q2.
IN4
IN7
(1) Operating at A-D conversion mode
The A-D conversion mode is set by setting the bit 3 of register Q2 to "0."
(2) Successive comparison register AD
Register AD stores the A-D conversion result of an analog input in
10-bit digital data format. The contents of the high-order 8 bits of
this register can be stored in register B and register A with the
TABAD instruction. The contents of the low-order 2 bits of this reg-
ister can be stored into the high-order 2 bits of register A with the
TALA instruction. However, do not execute this instruction during A-
D conversion.
When the contents of register AD is n, the logic value of the com-
parison voltage V
generated from the built-in DA converter can
ref
be obtained with the reference voltage V
mula:
Logic value of comparison voltage V
V
DD
V
=
n
ref
1024
n: The value of register AD (n = 0 to 1023)
(3) A-D conversion completion flag (ADF)
A-D conversion completion flag (ADF) is set to "1" when A-D con-
version completes. The state of ADF flag can be examined with the
skip instruction (SNZAD). Use the interrupt control register V2 to
select the interrupt or the skip instruction.
The ADF flag is cleared to "0" when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
1-42
Q1
2
0
0
0
0
1
1
1
1
/A
pin function selec-
2
IN6
by the following for-
DD
ref
4513/4514 Group User's Manual
at reset : 0000
2
0
This bit has no function, but read/write is enabled.
1
Q1
Q1
1
0
0
0
A
IN0
0
1
A
IN1
1
0
A
IN2
1
1
A
IN3
0
0
A
(Not available for the 4513 Group)
IN4
0
1
A
(Not available for the 4513 Group)
IN5
1
0
A
(Not available for the 4513 Group)
IN6
1
1
A
(Not available for the 4513 Group)
IN7
at reset : 0000
2
0
A-D conversion mode
1
Comparator mode
0
P4
, P4
(read/write enabled for the 4513 Group)
3
2
1
A
, A
/P4
, P4
(read/write enabled for the 4513 Group)
IN7
IN6
3
2
0
P4
(read/write enabled for the 4513 Group)
1
1
A
/P4
(read/write enabled for the 4513 Group)
IN5
1
0
P4
(read/write enabled for the 4513 Group)
0
1
A
/P4
(read/write enabled for the 4513 Group)
IN4
0
(4) A-D conversion start instruction (ADST)
A-D conversion starts when the ADST instruction is executed. The
conversion result is automatically stored in the register AD.
(5) A-D control register Q1
Register Q1 is used to select one of analog input pins. The 4513
Group does not have A
pins with register Q1.
(6) A-D control register Q2
Register Q2 is used to select the pin function of P4
A
, P4
/A
, and P4
IN5
2
IN6
lected when the bit 3 of register Q2 is "0," and the comparator
mode is selected when the bit 3 of register Q2 is "1." After set this
register, select the analog input with register Q1.
Even when register Q2 is used to set the pins for analog input,
P4
/A
–P4
/A
0
IN4
3
IN7
ingly, when any of them are used as I/O port P4 and others are
used as analog input pins, make sure to set the outputs of pins that
are set for analog input to "1." Also, for the port input, the port input
function of the pin functions as analog input is undefined.
at RAM back-up : state retained
Selected pins
at RAM back-up : state retained
–A
. Accordingly, do not select these
IN4
IN7
/A
. The A-D conversion mode is se-
3
IN7
continue to function as P4
–P4
0
R/W
R/W
/A
, P4
/
0
IN4
1
I/O. Accord-
3
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