Table 2.9.5 Pull-Up Control Register Pu0; Table 2.9.6 Interrupt Control Register I1 - Renesas 4513 User Manual

(2) Pull-up control register PU0
Pull-up control register PU0 controls the pull-up functions of ports P0
Set the contents of this register through register A with the TPU0A instruction. The TAPU0 instruction
can be used to transfer the contents of register PU0 to register A.
Table 2.9.5 shows the pull-up control register PU0.

Table 2.9.5 Pull-up control register PU0

Pull-up control register PU0
P i n s P 1
2
PU0
3
transistor control bit
P i n s P 1
0
PU0
2
transistor control bit
P i n s P 0
2
PU0
1
transistor control bit
P i n s P 0
0
PU0
0
transistor control bit
Note: "R" represents read enabled, and "W" represents write enabled.
(3) Interrupt control register I1
The interrupt valid waveform for INT0 pin/return level selection bit is assigned to bit 2, INT0 pin edge
detection circuit control bit is assigned to bit 1, and INT0 pin timer 1 control enable bit is assigned
to bit 0.
Set the contents of this register through register A with the TI1A instruction.
In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
Table 2.9.6 shows the interrupt control register I1.

Table 2.9.6 Interrupt control register I1

Interrupt control register I1
I1
Not used
3
Interrupt valid waveform for INT0
I1 pin/return level selection bit
2
(Note 2)
INT0 pin edge detection circuit
I1
1
control bit
INT0 pin
I1
0
timer 1 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled.
2: When the contents of I1
Accordingly, clear EXF0 flag with the SNZ0 instruction.
a n d P 1 p u l l - u p
3
a n d P 1 p u l l - u p
1
a n d P 0 p u l l - u p
3
a n d P 0 p u l l - u p
1
is changed, the external interrupt request flag EXF0 may be set.
2
4513/4514 Group User's Manual
at reset : 0000 at RAM back-up : state retained
2
Pull-up transistor OFF
0
Pull-up transistor ON
1
Pull-up transistor OFF
0
Pull-up transistor ON
1
Pull-up transistor OFF
0
Pull-up transistor ON
1
Pull-up transistor OFF
0
Pull-up transistor ON
1
at reset : 0000 at RAM back-up : state retained
2
0
This bit has no function, but read/write is enabled.
1
Falling waveform ("L" level of INT0 pin is recognized
0
with the SNZI0 instruction)/"L" level
Rising waveform ("H" level of INT0 pin is recognized
1
with the SNZI0 instruction)/"H" level
One-sided edge detected
0
1 Both edges detected
Disabled
0
Enabled
1
APPLICATION
2.9 RAM back-up
–P0 , P1 –P1 .
0 3 0 3
R/W
R/W
2-61