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Divistion circuit
(divided by 2)
X
IN
Data is set automatically from each reload
register when timer 1, 2, 3, or 4 underflows
(auto-reload function)
Notes 1: Timer 1 count start synchronous circuit is set
by the valid edge of P3
bits 1 (I1
) and 2 (I1
) of register I1.
1
2
2: Timer 3 count start synchronous circuit is set
by the valid edge of P3
bits 1 (I2
) and 2 (I2
) of register I2.
1
2
3: Count source is stopped by clearing to "0."
Fig. 19 Timers structure
Instruction clock
MR
3
Internal clock
1
generating circuit
0
(divided by 3)
I1
2
Falling
One-sided edge
detection circuit
0
P3
/INT0
0
1
Both edges
detection circuit
Rising
W1
(Note 3)
1
(TAB1)
W2
,W2
1
0
00
01
10
Not available
11
(TAB2)
I2
2
Falling
One-sided edge
detection circuit
0
P3
/INT1
1
1
Both edges
detection circuit
Rising
W3
,W3
1
0
W3
00
01
10
Not available
11
Not available
(TAB3)
W4
,W4
1
0
00
01
10
Not available
11
Not available
(TAB4)
Instruction clock
/INT0 pin selected by
0
WRST instruction
Reset signal
/INT1 pin selected by
1
4513/4514 Group User's Manual
FUNCTION BLOCK OPERATIONS
Prescaler
W1
3
W1
0
1/4
1/16
1
ORCLK
I1
1
0
(Note 1)
Q
S
1
I1
R
0
0
Timer 1 (8)
1
Reload register R1 (8)
T1AB
T1AB
(TR1AB)
Register B Register A
Timer 1 underflow signal
W2
(Note 3)
3
0
Timer 2 (8)
1
Reload register R2 (8)
(T2AB)
Register B Register A
Timer 2 underflow signal
I2
1
0
(Note 2)
S
Q
1
I2
R
0
(Note 3)
3
0
Timer 3 (8)
1
Reload register R3 (8)
T3AB
(TR3AB)
Register B Register A
Timer 3 underflow signal
W4
(Note 3)
3
0
Timer 4 (8)
1
Reload register R4 (8)
(T4AB)
Register B Register A
16-bit timer (WDT)
1 - - - - - - - - - - - 15 16
S
Q
WEF
R
HARDWARE
2
0
1
W1
0
1
0
T1F
T2F
W3
2
1
0
T3F
T3AB
T4F
System reset
WDF1 WDF2
Timer 1
interrupt
Timer 2
interrupt
Timer 3
interrupt
Timer 4
interrupt
1-31
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