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PORT BLOCK DIAGRAMS (continued)
Direction register FR0i
OP5A instruction
Register A
Register Y
SD instruction
RD instruction
Register Y
SD instruction
RD instruction
Timer 1 underflow signal divided by 2 or
signal of AND operation between
timer 1 underflow signal divided by 2 and
timer 2 underflow signal divided by 2
Register Y
SD instruction
RD instruction
Timer 3 underflow signal divided by 2 or
signal of AND operation between
timer 3 underflow signal divided by 2 and
timer 4 underflow signal divided by 2
Ai
D
Q
T
IAP5 instruction
Skip decision
Decoder
(SZD instruction)
CLD instruction
Skip decision (SZD instruction)
Clock input for timer 2 event count
Decoder
CLD instruction
S
R
Skip decision (SZD instruction)
Clock input for timer 4 event count
Decoder
CLD instruction
S
R
4513/4514 Group User's Manual
P5
D
0
S
R
Q
W6
0
0
Q
1
W6
2
0
Q
1
This symbol represents a parasitic diode on the port.
•
• Applied potential to ports D
• i represents 0, 1, 2, or 3.
• The 4513 Group does not have port P5.
HARDWARE
PIN DESCRIPTION
–P5
0
3
–D
5
D
/CNTR0
6
D
/CNTR1
7
–D
must be 12 V.
0
7
1-15
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