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HARDWARE
FUNCTION BLOCK OPERATIONS
Table 10 Timer control registers
Timer control register W1
W1
Prescaler control bit
3
W1
Prescaler dividing ratio selection bit
2
W1
Timer 1 control bit
1
Timer 1 count start synchronous circuit
W1
0
control bit
Timer control register W2
W2
Timer 2 control bit
3
W2
Not used
2
W2
1
Timer 2 count source selection bits
W2
0
Timer control register W3
W3
Timer 3 control bit
3
Timer 3 count start synchronous circuit
W3
2
control bit
W3
1
Timer 3 count source selection bits
W3
0
Timer control register W4
W4
Timer 4 control bit
3
W4
Not used
2
W4
1
Timer 4 count source selection bits
W4
0
Timer control register W6
W6
CNTR1 output control bit
3
W6
D
/CNTR1 function selection bit
2
7
W6
CNTR0 output control bit
1
W6
D
/CNTR0 output control bit
0
6
Note: "R" represents read enabled, and "W" represents write enabled.
1-32
at reset : 0000
at reset : 0000
2
2
0
Stop (state initialized)
1
Operating
0
Instruction clock divided by 4
1
Instruction clock divided by 16
0
Stop (state retained)
1
Operating
0
Count start synchronous circuit not selected
1
Count start synchronous circuit selected
at reset : 0000
2
0
Stop (state retained)
1
Operating
0
This bit has no function, but read/write is enabled.
1
W2
W2
1
0
0
0
Timer 1 underflow signal
0
1
Prescaler output
1
0
CNTR0 input
1
1
16 bit timer (WDT) underflow signal
at reset : 0000
2
0
Stop (state retained)
1
Operating
0
Count start synchronous circuit not selected
1
Count start synchronous circuit selected
W3
W3
1
0
0
0
Timer 2 underflow signal
0
1
Prescaler output
1
0
Not available
1
1
Not available
at reset : 0000
2
0
Stop (state retained)
1
Operating
0
This bit has no function, but read/write is enabled.
1
W4
W4
1
0
0
0
Timer 3 underflow signal
0
1
Prescaler output
1
0
CNTR1 input
1
1
Not available
at reset : 0000
2
0
Timer 3 underflow signal output divided by 2
1
CNTR1 output control by timer 4 underflow signal divided by 2
0
D
(I/O)/CNTR1 input
7
1
CNTR1 (I/O)/D
0
Timer 1 underflow signal output divided by 2
1
CNTR0 output control by timer 2 underflow signal divided by 2
0
D
(I/O)/CNTR0 input
6
1
CNTR0 (I/O)/D
4513/4514 Group User's Manual
at RAM back-up : 0000
at RAM back-up : 0000
at RAM back-up : state retained
Count source
at RAM back-up : state retained
Count source
at RAM back-up : state retained
Count source
at RAM back-up : state retained
(input)
7
(input)
6
R/W
R/W
2
2
R/W
R/W
R/W
R/W
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