Related Registers; Table 2.3.1 Interrupt Control Register V1; Table 2.3.2 Interrupt Control Register V2 - Renesas 4513 User Manual

4500 series 4-bit single-chip microcomputer
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2.3.2 Related registers

(1) Interrupt control register V1
The timer 1 interrupt enable bit is assigned to bit 2, and the timer 2 interrupt enable bit is assigned
to bit 3.
Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
Table 2.3.1 shows the interrupt control register V1.

Table 2.3.1 Interrupt control register V1

Interrupt control register V1
V1
Timer 2 interrupt enable bit
3
V1
Timer 1 interrupt enable bit
2
V1
External 1 interrupt enable bit
1
V1
External 0 interrupt enable bit
0
Notes 1: "R" represents read enabled, and "W" represents write enabled.
2: When timer is used, V1
(2) Interrupt control register V2
The timer 3 interrupt enable bit is assigned to bit 0, and the timer 4 interrupt enable bit is assigned
to bit 1.
Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction
can be used to transfer the contents of register V2 to register A.
Table 2.3.2 shows the interrupt control register V2.

Table 2.3.2 Interrupt control register V2

Interrupt control register V2
V2
Serial I/O interrupt enable bit
3
V2
A-D interrupt enable bit
2
V2
Timer 4 interrupt enable bit
1
V2
Timer 3 interrupt enable bit
0
Notes 1: "R" represents read enabled, and "W" represents write enabled.
2: When timer is used, V2
at reset : 0000
Interrupt disabled (SNZT2 instruction is valid)
0
Interrupt enabled (SNZT2 instruction is invalid)
1
Interrupt disabled (SNZT1 instruction is valid)
0
Interrupt enabled (SNZT1 instruction is invalid)
1
Interrupt disabled (SNZ1 instruction is valid)
0
Interrupt enabled (SNZ1 instruction is invalid)
1
Interrupt disabled (SNZ0 instruction is valid)
0
Interrupt enabled (SNZ0 instruction is invalid)
1
and V1
are not used.
1
0
at reset : 0000
Interrupt disabled (SNZSI instruction is valid)
0
Interrupt enabled (SNZSI instruction is invalid)
1
Interrupt disabled (SNZAD instruction is valid)
0
Interrupt enabled (SNZAD instruction is invalid)
1
Interrupt disabled (SNZT4 instruction is valid)
0
Interrupt enabled (SNZT4 instruction is invalid)
1
Interrupt disabled (SNZT3 instruction is valid)
0
Interrupt enabled (SNZT3 instruction is invalid)
1
and V2
are not used.
2
3
4513/4514 Group User's Manual
APPLICATION
at RAM back-up : 0000
2
at RAM back-up : 0000
2
2.3 Timers
R/W
2
R/W
2
2-27

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