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HARDWARE
FUNCTION BLOCK OPERATIONS
Table 13 Processing sequence of data transfer from master to slave
Master (transmission)
[Initial setting]
• Setting the serial I/O mode register J1 and inter-
rupt control register V2 shown in Figure 24.
TJ1A and TV2A instructions
• Setting the port received the reception enable
signal (S
) to the input mode.
RDY
(Port D
is used in this example)
5
SD instruction
* [Transmission enable state]
• Storing transmission data to serial I/O register SI.
TSIAB instruction
[Transmission]
•Check port D
is "L" level.
5
SZD instruction
•Serial transfer starts.
SST instruction
•Check transmission completes.
SNZSI instruction
•Wait (timing when continuously transferring)
1-byte data is serially transferred on this process. Subsequently, data
can be transferred continuously by repeating the process from *.
When an external clock is selected as a synchronous clock, the
clock is not controlled internally. Control the clock externally be-
cause serial transfer is performed as long as clock is externally
input. (Unlike an internal clock, an external clock is not stopped
when serial transfer is completed.) However, the SIOF flag is set to
"1" when the clock is counted 8 times after executing the SST in-
struction. Be sure to set the initial level of the external clock to "H."
1-40
[Initial setting]
• Setting serial I/O mode register J1, and interrupt control register V2 shown in
Figure 24.
• Setting the port transmitted the reception enable signal (S
"H" level (reception impossible).
(Port D
is used in this example)
5
*[Reception enable state]
• The SIOF flag is cleared to "0."
• "L" level (reception possible) is output from port D
[Reception]
• Check reception completes.
• "H" level is output from port D
[Data processing]
4513/4514 Group User's Manual
Slave (reception)
TJ1A and TV2A instructions
SD instruction
SST instruction
.
5
RD instruction
SNZSI instruction
.
5
SD instruction
) and outputting
RDY
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