Table 2.2.3 Interrupt Control Register I1; Table 2.2.4 Interrupt Control Register I2 - Renesas 4513 User Manual

(5) Interrupt control register I1
The INT0 pin timer 1 control enable bit is assigned to bit 0, INT0 pin edge detection circuit control
bit is assigned to bit 1, and interrupt valid waveform for INT0 pin/return level selection bit is assigned
to bit 2.
Set the contents of this register through register A with the TI1A instruction.
In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
Table 2.2.3 shows the interrupt control register I1.

Table 2.2.3 Interrupt control register I1

Interrupt control register I1
I1 Not used
3
Interrupt valid waveform for INT0
I1 pin/return level selection bit
2
(Note 2)
INT0 pin edge detection circuit
I1
1
control bit
INT0 pin
I1
0
timer 1 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled.
2: When the contents of I1
Accordingly, clear EXF0 flag with the SNZ0 instruction.
(6) Interrupt control register I2
The INT1 pin timer 3 control enable bit is assigned to bit 0, the INT1 pin edge detection circuit control
bit is assigned to bit 1 and the interrupt valid waveform for INT1 pin/return level selection bit is
assigned to bit 2.
Set the contents of this register through register A with the TI2A instruction.
In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A.
Table 2.2.4 shows the interrupt control register I2.

Table 2.2.4 Interrupt control register I2

Interrupt control register I2
I2 Not used
3
Interrupt valid waveform for INT1
I2 pin/return level selection bit
2
(Note 2)
INT1 pin edge detection circuit
I2
1
control bit
INT1 pin
I2
0
timer 3 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled.
2: When the contents of I2
Accordingly, clear EXF1 flag with the SNZ1 instruction.
at reset : 0000
0
This bit has no function, but read/write is enabled.
1
Falling waveform ("L" level of INT0 pin is recognized
0
with the SNZI0 instruction)/"L" level
Rising waveform ("H" level of INT0 pin is recognized
1
with the SNZI0 instruction)/"H" level
One-sided edge detected
0
1 Both edges detected
0 Disabled
Enabled
1
is changed, the external interrupt request flag EXF0 may be set.
2
at reset : 0000
0
This bit has no function, but read/write is enabled.
1
Falling waveform ("L" level of INT1 pin is recognized
0
with the SNZI1 instruction)/"L" level
Rising waveform ("H" level of INT1 pin is recognized
1
with the SNZI1 instruction)/"H" level
One-sided edge detected
0
Both edges detected
1
Disabled
0
Enabled
1
is changed, the external interrupt request flag EXF1 may be set.
2
4513/4514 Group User's Manual
APPLICATION
at RAM back-up : state retained
2
at RAM back-up : state retained
2
2.2 Interrupts
R/W
R/W
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