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When transmitting (D
Serial I/O register (SI)
D
D
7
6
D
D
7
6
D
7
Fig. 23 Serial I/O register state when transferring
(1) Serial I/O register SI
Serial I/O register SI is the 8-bit data transfer serial/parallel conver-
sion register. Data can be set to register SI through registers A and
B with the TSIAB instruction. The contents of register A is transmit-
ted to the low-order 4 bits of register SI, and the contents of
register B is transmitted to the high-order 4 bits of register SI.
During transmission, each bit data is transmitted LSB first from the
lowermost bit (bit 0) of register SI, and during reception, each bit
data is received LSB first to register SI starting from the topmost bit
(bit 7).
When register SI is used as a work register without using serial I/O,
pull up the S
pin or set the pin function to an input port P2
CK
( 2 ) S e r i a l I / O t r a n s m i s s i o n / r e c e p t i o n
completion flag (SIOF)
Serial I/O transmission/reception completion flag (SIOF) is set to
"1" when serial data transmission or reception completes. The
state of SIOF flag can be examined with the skip instruction
(SNZSI). Use the interrupt control register V2 to select the inter-
rupt or the skip instruction.
The SIOF flag is cleared to "0" when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
–D
: transfer data)
7
0
S
OUT
D
D
D
D
D
D
5
4
3
2
1
0
D
D
D
D
D
D
5
4
3
2
1
0
Transfer data to be set
D
D
D
D
D
D
6
5
4
3
2
1
D
D
D
D
D
D
7
6
5
4
3
2
4513/4514 Group User's Manual
FUNCTION BLOCK OPERATIONS
When receiving
S
pin
S
pin
IN
OUT
pin
S
pin
IN
Transfer started
D
D
D
Transfer completed
(3) Serial I/O start instruction (SST)
When the SST instruction is executed, the SIOF flag is cleared to
"0" and then serial I/O transmission/reception is started.
(4) Serial I/O mode register J1
Register J1 controls the synchronous clock, P2
and P2
/S
pin function. Set the contents of this register through
2
IN
register A with the TJ1A instruction. The TAJ1 instruction can be
used to transfer the contents of register J1 to register A.
.
0
HARDWARE
Serial I/O register (SI)
0
D
1
0
D
D
D
D
D
D
D
7
6
5
4
3
2
1
0
/S
, P2
/S
0
CK
1
OUT
1-37
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