Differential Clock Routing Diagram (Section 'A', 'C', & 'D'); Non-Differential Clock Routing Diagram (Section 'B'); Termination For Direct Rambus* Clocking Signals Cfm/Cfm - Intel VC820 - Desktop Board Motherboard Design Manual

For the line section labeled 'D' (DRCG to Last RIMM) the CTM/CTM# must be length matched
within ±2 mils (exactly is recommended), and for the section labeled 'C', ±2 mil trace length
matching is required for the CFM/CFM# signals.
Note: Total trace length matching for the entire CTM/CTM# signal trace (Sections A+B+D) and for the
CFM/CFM# signal trace (Sections A+B) is ±2 mils (exact length matching is recommended).
Figure 4-6. Differential Clock Routing Diagram (Section 'A', 'C', & 'D')
22 mils
Ground
Figure 4-7. Non-Differential Clock Routing Diagram (Section 'B')
10 mils
Ground
The CFM/CFM# differential pair signals require termination using either 27 Ω 1% or 28 Ω 2%
resistors and a 0.1 uF capacitor as shown in
Figure 4-8. Termination for Direct Rambus* Clocking Signals CFM/CFM#
®
Intel 820 Chipset Design Guide
14 mils
CLOCK
6 mils
4.5 mils
Ground/Power Plane
6 mils
4.5 mils
Ground/Power Plane
CFM
CFM#
14 mils
CLOCK#
6 mils
18 mils
CLOCK/CLOCK#
6 mils
Figure 4-8.
R1
28 Ω 2%
or
27 Ω 1%
R2
0 .1 uF
28 Ω 2%
or
27 Ω 1%
22 mils
Ground
6 mils
4.5 mils
dif lk
10 mils
Ground
4.5 mils
C1
Clocking
2.1 mils
1.4 mils
t d
2.1 mils
1.4 mils
4-9