Xilinx RocketIO User Manual page 27

List of Available Ports
Table 3-1: GT_CUSTOM
GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued)
Port
RXPOLARITY
RXREALIGN
RXRECCLK
RXRESET
(3)
RXRUNDISP
RXUSRCLK
RXUSRCLK2
TXBUFERR
(3)
TXBYPASS8B10B
(3)
TXCHARDISPMODE
(3)
TXCHARDISPVAL
(3)
TXCHARISK
(3)
TXDATA
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
(1)
, GT_AURORA, GT_FIBRE_CHAN
Port
I/O
Size
I 1 Similar to TXPOLARITY, but for RXN and RXP. When deasserted, assumes
regular polarity. When asserted, reverses polarity.
O 1 Signal from the PMA denoting that the byte alignment with the serial data
stream changed due to a comma detection. Asserted High when alignment
occurs.
O 1 Recovered clock that is divided by 20.
I 1 Synchronous RX system reset that "recenters" the receive elastic buffer. It
also resets 8B/10B decoder, comma detect, channel bonding, clock
correction logic, and other internal receive registers. It does not reset the
receiver PLL.
O 1, 2, 4 Signals the running disparity (0 = negative, 1 = positive) in the received
serial data. If 8B/10B encoding is bypassed, it remains as the second bit
received (Bit "b") of the 10-bit encoded data (see
I 1 Clock from a DCM that is used for reading the RX elastic buffer. It also
clocks CHBONDI and CHBONDO in and out of the transceiver. Typically,
the same as TXUSRCLK.
I 1 Clock output from a DCM that clocks the receiver data and status between
the transceiver and the FPGA core. Typically the same as TXUSRCLK2.
The relationship between RXUSRCLK and RXUSRCLK2 depends on the
width of the RXDATA.
O 1 Provides status of the transmission FIFO. If asserted High, an
overflow/underflow has occurred. When this bit becomes set, it can only
be reset by asserting TXRESET.
I 1, 2, 4 This control signal determines whether the 8B/10B encoding is enabled or
bypassed. If the signal is asserted High, the encoding is bypassed. This
creates a 10-bit interface to the FPGA core. See the 8B/10B section for more
details.
I 1, 2, 4 If 8B/10B encoding is enabled, this bus determines what mode of disparity
is to be sent. When 8B/10B is bypassed, this becomes the first bit
transmitted (Bit "a") of the 10-bit encoded TXDATA bus section (see
Figure 3-10) for each byte specified by the byte-mapping.
I 1, 2, 4 If 8B/10B encoding is enabled, this bus determines what type of disparity
is to be sent. When 8B/10B is bypassed, this becomes the second bit
transmitted (Bit "b") of the 10-bit encoded TXDATA bus section (see
Figure 3-10) for each byte specified by the byte-mapping section.
I 1, 2, 4 If 8B/10B encoding is enabled, this control bus determines if the
transmitted data is a "K" character or a Data character. A logic High
indicating a K-character.
I 8,16,32 Transmit data that can be 1, 2, or 4 bytes wide, depending on the primitive
used. TXDATA [7:0] is always the last byte transmitted. The position of the
first byte depends on selected TX data path width.
(2)
, GT_ETHERNET
Definition
www.xilinx.com
1-800-255-7778
(2)
,
Figure 3-11).
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