Xilinx RocketIO User Manual page 45

Clocking
Verilog Template
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
port map (
I => REFCLKIN,
O => REFCLK
U2_BUFG: BUFG
port map (
I => CLK0_W,
O => USRCLK_M
);
U3_BUFG: BUFG
port map (
I => CLKDV_W,
O => USRCLK2_M
);
end FOUR_BYTE_CLK_arch;
// Module: FOUR_BYTE_CLK
// Description: Verilog Submodule
// DCM for 4-byte GT
//
// Device: Virtex-II Pro Family
module FOUR_BYTE_CLK(
REFCLKIN,
REFCLK,
USRCLK_M,
USRCLK2_M,
DCM_LOCKED
input REFCLKIN;
output REFCLK;
output USRCLK_M;
output USRCLK2_M;
output DCM_LOCKED;
wire REFCLKIN;
wire REFCLK;
wire USRCLK_M;
wire USRCLK2_M;
wire DCM_LOCKED;
wire REFCLKINBUF;
wire clkdv2;
wire clk_i;
DCM dcm1 (
.CLKFB
.CLKIN
1'b0 ),
.PSCLK
.PSEN
.PSINCDEC
.RST
.CLK0
.CLK90
.CLK180
.CLK270
.CLK2X
www.xilinx.com
1-800-255-7778
);
);
( USRCLK_M ),
( REFCLKINBUF ) ,
( 1'b0 ),
( 1'b0 ),
( 1'b0 ),
( 1'b0 ),
( clk_i ),
( ),
( ),
( ),
( ),
R
.DSSEN (
45