Xilinx RocketIO User Manual page 44

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port (
I : in std_logic;
O : out std_logic
);
end component;
--
component IBUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
--
component DCM
port (
CLKIN
: in std_logic;
CLKFB
: in std_logic;
DSSEN
: in std_logic;
PSINCDEC
: in std_logic;
PSEN
: in std_logic;
PSCLK
: in std_logic;
RST
: in std_logic;
CLK0
: out std_logic;
CLK90
: out std_logic;
CLK180
: out std_logic;
CLK270
: out std_logic;
CLK2X
: out std_logic;
CLK2X180
: out std_logic;
CLKDV
: out std_logic;
CLKFX
: out std_logic;
CLKFX180
: out std_logic;
LOCKED
: out std_logic;
PSDONE
: out std_logic;
STATUS
: out std_logic_vector ( 7 downto 0 )
);
end component;
--
-- Signal Declarations:
--
signal GND
: std_logic;
signal CLK0_W
: std_logic;
signal CLKDV_W
: std_logic;
begin
GND
<= '0';
-- DCM Instantiation
U_DCM: DCM
port map (
CLKIN
=>
DSSEN
=>
PSINCDEC
=>
PSEN
=>
PSCLK
=>
RST
=>
CLK0
=>
CLKDV
=>
LOCKED
=>
);
-- BUFG Instantiation
U_BUFG: IBUFG
www.xilinx.com
1-800-255-7778
Chapter 3: Digital Design Considerations
REFCLK,
CLKFB
=>
GND,
GND,
GND,
GND,
RST,
CLK0_W,
CLKDV_W,
LOCK
RocketIO™ Transceiver User Guide
CLK0_W,
UG024 (v1.5) October 16, 2002

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