Xilinx RocketIO User Manual page 3

RocketIO™ Transceiver User Guide
UG024 (v1.5) October 16, 2002
The following table shows the revision history for this document.
Date Version
11/20/01 1.0
01/23/02 1.1
02/25/02 1.2
07/11/02 1.3
09/27/02 1.4
10/16/02 1.5
UG024 (v1.5) October 16, 2002
Initial Xilinx release.
Updated for typographical and other errors found during review.
Part of Virtex-II Pro™ Developer's Kit (March 2002 Release)
Updated
PCB Design Requirements, Chapter
changed Cell Models to Appendix B.
• Added additional
IMPORTANT NOTES
Chapter 1
• Added material in section
• Added section Other Important Design Notes, Chapter 3
• New pre-emphasis eye diagrams in section
• Numerous parameter additions previously shown as "TBD" in
Chapter 5
• Corrected pinouts in
Constraints rows GT_X0_Y0 and GT_X0_Y1.
• Corrected section CRC Latency
TXUSRCLK and RXUSRCLK cycles.
• Corrected sequence of packet elements in
www.xilinx.com
Revision
4. Added Timing Model as Appendix A,
regarding ISE revisions at the beginning of
CRC Operation, Chapter 3
Pre-emphasis Techniques, Chapter 4
Table 5-2, FF1152 package, device column 2VP20/30, LOC
and Table 3-15
Figure
1-800-255-7778
MGT Package Pins,
to express latency in terms of
3-16.
RocketIO™ Transceiver User Guide