Xilinx RocketIO User Manual page 41

Clocking
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
);
end component;
--
component DCM
port (
CLKIN : in std_logic;
CLKFB : in std_logic;
DSSEN : in std_logic;
PSINCDEC : in std_logic;
PSEN : in std_logic;
PSCLK : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector ( 7 downto 0 )
);
end component;
--
-- Signal Declarations:
--
signal GND : std_logic;
signal CLK0_W : std_logic;
signal CLK1X_W : std_logic;
begin
GND <= '0';
--
CLK1X <= CLK1X_W;
--
-- DCM Instantiation
U_DCM: DCM
port map (
CLKIN =>
CLKFB =>
DSSEN =>
PSINCDEC =>
PSEN =>
PSCLK =>
RST =>
CLK0 =>
LOCKED =>
);
--
-- BUFG Instantiation
U_BUFG: IBUFG
port map (
I => REFCLKIN,
O => REFCLK
);
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REFCLK,
USRCLK_M,
GND,
GND,
GND,
GND,
RST,
CLK0_W,
LOCK
R
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