Xilinx RocketIO User Manual page 48

R
Verilog Template
48
CLK1X <= CLK1X_W;
--
-- DCM Instantiation
U_DCM: DCM
port map (
CLKIN =>
CLKFB =>
DSSEN =>
PSINCDEC =>
PSEN =>
PSCLK =>
RST =>
CLK0 =>
CLK2X180 =>
LOCKED =>
);
-- BUFG Instantiation
U_BUFG: IBUFG
port map (
I => REFCLKIN,
O => REFCLK
);
U2_BUFG: BUFG
port map (
I => CLK0_W,
O => USRCLK_M
);
U4_BUFG: BUFG
port map (
I => CLK2X180_W,
O => USRCLK2
);
end ONE_BYTE_CLK_arch;
// Module: ONE_BYTE_CLK
// Description: Verilog Submodule
// DCM for 1-byte GT
//
// Device: Virtex-II Pro Family
module ONE_BYTE_CLK (
REFCLKIN,
REFCLK,
USRCLK_M,
USRCLK2_M,
DCM_LOCKED
);
input REFCLKIN;
output REFCLK;
output USRCLK_M;
output USRCLK2_M;
output DCM_LOCKED;
wire REFCLKIN;
www.xilinx.com
1-800-255-7778
Chapter 3: Digital Design Considerations
REFCLK,
USRCLK_M,
GND,
GND,
GND,
GND,
RST,
CLK0_W,
CLK2X180_W,
LOCK
RocketIO™ Transceiver User Guide
UG024 (v1.5) October 16, 2002