Xilinx RocketIO User Manual page 80

R
80
-- are aligned to the MSB position
-- [31:24]. The module assumes ALIGN_COMMA_MSB is TRUE,
-- so that the comma
-- is already aligned to [31:24] or [15:8].
--
-- Outputs
--
-- aligned_data[31:0] -- Properly aligned 32-std_logic ALIGNED_DATA
-- sync -- Indicator that aligned_data is properly aligned
-- aligned_rxisk[3:0] -properly aligned 4-std_logic RXCHARISK
-- Inputs - These are all RocketIO inputs or outputs
-- as indicated:
--
-- usrclk2 -- RXUSRCLK2
-- rxreset -- RXRESET
-- rxdata[31:0] RXDATA[31:0] -- (commas aligned to
--
-- rxisk[3:0] - RXCHARISK[3:0]
-- rxrealign -- RXREALIGN
-- rxcommadet -- RXCOMMADET
-- rxchariscomma3 -- RXCHARISCOMMA[3]
-- rxchariscomma1 -- RXCHARISCOMMA[1]
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.Numeric_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY align_comma_32 IS
PORT (
aligned_data
aligned_rxisk
sync
usrclk2
rxreset
rxdata
rxisk
rxrealign
rxcommadet
rxchariscomma3
rxchariscomma1
END ENTITY align_comma_32;
ARCHITECTURE translated OF align_comma_32 IS
SIGNAL rxdata_reg
SIGNAL rxisk_reg
SIGNAL byte_sync
SIGNAL wait_to_sync
SIGNAL count
SIGNAL rxdata_hold
SIGNAL rxisk_hold
SIGNAL sync_hold
BEGIN
aligned_data <= rxdata_hold;
aligned_rxisk <= rxisk_hold;
sync <= sync_hold;
-- This process maintains wait_to_sync and count,
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Chapter 3: Digital Design Considerations
[31:24] or [15:8])
: OUT std_logic_vector(31 DOWNTO 0);
: OUT std_logic_vector(3 DOWNTO 0);
: OUT std_logic;
: IN std_logic;
: IN std_logic;
: IN std_logic_vector(31 DOWNTO 0);
: IN std_logic_vector(3 DOWNTO 0);
: IN std_logic;
: IN std_logic;
: IN std_logic;
: IN std_logic);
: std_logic_vector(15 DOWNTO 0);
: std_logic_vector(1 DOWNTO 0);
: std_logic;
: std_logic_vector(3 DOWNTO 0);
: std_logic;
: std_logic_vector(31 DOWNTO 0);
: std_logic_vector(3 DOWNTO 0);
: std_logic;
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide