Xilinx RocketIO User Manual page 28

R
Table 3-1: GT_CUSTOM
GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued)
Port
TXFORCECRCERR
TXINHIBIT
(3)
TXKERR
(4)
TXN
(4)
TXP
TXPOLARITY
TXRESET
(3)
TXRUNDISP
TXUSRCLK
TXUSRCLK2
Notes:
1. The GT_CUSTOM ports are always the maximum port size.
2. GT_FIBRE_CHAN and GT_ETHERNET ports do not have the three CHBOND** or ENCHANSYNC ports.
3. The port size changes with relation to the primitive selected, and also correlates to the byte mapping.
4. External ports only accessible from package pins.
5. Will be available in ISE 5.1.
28
(1)
, GT_AURORA, GT_FIBRE_CHAN
Port
I/O
Size
I 1 Specifies whether to insert error in computed CRC.
When TXFORCECRCERR = TRUE, the transmitter corrupts the correctly
computed CRC value by XORing with the bits specified in attribute
TX_CRC_FORCE_VALUE. This input can be used to test detection of CRC
errors at the receiver.
I 1 If a logic High, the TX differential pairs are forced to be a constant 1/0.
TXN = 1, TXP = 0
O 1, 2, 4 If 8B/10B encoding is enabled, this signal indicates (asserted High) when
the "K" character to be transmitted is not a valid "K" character. Bits
correspond to the byte-mapping scheme.
O 1 Transmit differential port (FPGA external)
O 1 Transmit differential port (FPGA external)
I 1 Specifies whether or not to invert the final transmitter output. Able to
reverse the polarity on the TXN and TXP lines. Deasserted sets regular
polarity. Asserted reverses polarity.
I 1 Synchronous TX system reset that "recenters" the transmit elastic buffer. It
also resets 8B/10B encoder and other internal transmission registers. It
does not reset the transmission PLL.
O 1, 2, 4 Signals the running disparity after this byte is encoded. Zero equals
negative disparity and positive disparity for a one.
I 1 Clock output from a DCM that is clocked with the REFCLK (or other
reference clock). This clock is used for writing the TX buffer and is
frequency-locked to the REFCLK.
I 1 Clock output from a DCM that clocks transmission data and status and
reconfiguration data between the transceiver an the FPGA core. The ratio
between the TXUSRCLK and TXUSRCLK2 depends on the width of the
TXDATA.
Chapter 3: Digital Design Considerations
(2)
, GT_ETHERNET
Definition
www.xilinx.com
1-800-255-7778
(2)
,
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide