Xilinx RocketIO User Manual page 6

R
BREFCLK ................................................................................................................................ 50
Half-Rate Clocking Scheme ................................................................................................. 52
Multiplexed Clocking Scheme............................................................................................. 53
Data Path Latency ................................................................................................................. 53
Clock Dependency ................................................................................................................ 54
Resets
............................................................................................................................................ 54
RocketIO Transceiver Instantiations
PLL Operation and Clock Recovery
Clock Correction Count........................................................................................................ 56
RX_LOSS_OF_SYNC_FSM .................................................................................................. 57
8B/10B Operation.................................................................................................................. 57
Vitesse Disparity Example ................................................................................................... 59
Status Signals
8B/10B Encoding
8B/10B Serial Output Format.............................................................................................. 69
CRC Operation
CRC Generation..................................................................................................................... 70
CRC Latency........................................................................................................................... 71
CRC Limitations .................................................................................................................... 71
CRC Modes............................................................................................................................. 71
Channel Bonding (Channel-to-Channel Alignment)
Other Important Design Notes
Receive Data Path 32-bit Alignment................................................................................... 75
32-bit Alignment Design ...................................................................................................... 76
Chapter 4: Analog Design Considerations
Serial I/O Description
Pre-emphasis Techniques
Differential Receiver
Jitter
............................................................................................................................................... 87
Total Jitter (DJ + RJ)............................................................................................................... 87
Clock and Data Recovery
PCB Design Requirements
Power Conditioning.............................................................................................................. 89
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Transmitter Latency
................................................................................................................ 54
Receiver Latency
.......................................................................................................... 56
HDL Code Examples
SYNC_ACQUIRED (RXLOSSOFSYNC = 00)
RESYNC (RXLOSSOFSYNC = 01)
LOSS_OF_SYNC (RXLOSSOFSYNC = 10)
Transmitting Vitesse Channel Bonding Sequence
Receiving Vitesse Channel Bonding Sequence
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HDL Code Examples: Transceiver Bypassing of 8B/10B Encoding
......................................................................................................................... 70
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USER_MODE
............................................................................................................. 72
FIBRECHANNEL
...................................................................................................................... 72
ETHERNET
................................................................................................................... 72
INFINIBAND
HDL Code Examples: Channel Bonding
.............................................................................................................................. 76
Verilog
............................................................................................................................... 79
VHDL
........................................................................................................... 83
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Deterministic Jitter (DJ)
.............................................................................................................. 87
Random Jitter (RJ)
..................................................................................................... 87
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Voltage Regulation
................................................................................................................. 90
Passive Filtering
www.xilinx.com
1-800-255-7778
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UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide