200 Mhz 2.5V Lvds Oscillator; Differential Sma Mrcc Pin Inputs - Xilinx Virtex-7 VC7203 User Manual

Chapter 1: VC7203 Board Features and Operation
The switch settings for selecting each address are shown in
Table 1-6: SW8 DIP Switch Configuration

200 MHz 2.5V LVDS Oscillator

U35 (callout 11,
The VC7203 board has one 200 MHz 2.5V LVDS oscillator (U35) connected to multi-region
clock capable (MRCC) inputs on the FPGA.
LVDS oscillator.
Table 1-7: LVDS Oscillator MRCC Connections
FPGA (U1)
Pin Function
E19 SYSTEM CLOCK_P
E18 SYSTEM CLOCK_N

Differential SMA MRCC Pin Inputs

Callout 30,
The VC7203 board provides two pairs of differential SMA transceiver clock inputs that can
be used for connecting to an external function generator. The FPGA MRCC pins are
connected to the SMA connectors as shown in
Table 1-8: Differential SMA Clock Connections
Pin Function
H19 USER CLOCK_1_P
G18 USER CLOCK_1_N
K39 USER CLOCK_2_P
K40 USER CLOCK_2_N
18
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Configuration Bitstream Address
0
1
2
3
4
5
6
7
Figure 1-2).
Direction I/O Standard
Input LVDS
Input LVDS
Figure 1-2.
FPGA (U1)
Direction I/O Standard
Input
Input
Input
Input
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ADR2
ON
ON
ON
ON
OFF
OFF
OFF
OFF
Table 1-7 lists the FPGA pin connections to the
Schematic
Net Name
Pin
LVDS_OSC_P 4 200 MHz LVDS oscillator
LVDS_OSC_N 5 201 MHz LVDS oscillator
Table 1-8.
Schematic Net Name
LVDS_25 CLK_DIFF_1_P
LVDS_25 CLK_DIFF_1_N
LVDS_25 CLK_DIFF_2_P
LVDS_25 CLK_DIFF_2_N
VC7203 GTX Transceiver Characterization Board
Table 1-6.
ADR1 ADR0
ON ON
ON OFF
OFF ON
OFF OFF
ON ON
ON OFF
OFF ON
OFF OFF
Device (U35)
Function Direction
Output
Output
SMA Connector
J99
J100
J98
J101
UG957 (v1.3) October 17, 2014