200 Mhz 2.5V Lvds Oscillator; 200 Mhz 2.5V Lvds Oscillator; Differential Sma Mrcc Pin Inputs; Superclock-2 Module - Xilinx VC7203 User Manual

Chapter 1: VC7203 Board Features and Operation
Table 1-6: SW8 DIP Switch Configuration (Cont'd)

200 MHz 2.5V LVDS Oscillator

U35 (callout 11,
The VC7203 board has one 200 MHz 2.5V LVDS oscillator (U35) connected to multi-region
clock capable (MRCC) inputs on the FPGA.
LVDS oscillator.
Table 1-7: LVDS Oscillator MRCC Connections

Differential SMA MRCC Pin Inputs

Callout 30,
The VC7203 board provides two pairs of differential SMA transceiver clock inputs that can
be used for connecting to an external function generator. The FPGA MRCC pins are
connected to the SMA connectors as shown in
Table 1-8: Differential SMA Clock Connections

SuperClock-2 Module

Callout 10,
The SuperClock-2 module connects to the clock module interface connector (J82) and
provides a programmable, low-noise and low-jitter clock source for the VC7203 board. The
clock module maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock
pair, and 1 reset pin.
18
Configuration Bitstream
Address
2
3
4
5
6
7
Figure 1-2).
U1 FPGA Pin Net Name
E19 IO_LVDS_OSC_P
E18 IO_LVDS_OSC_N
Figure 1-2.
U1 FPGA Pin Net Name
H19 CLK_DIFF_1_P
G18 CLK_DIFF_1_N
K39 CLK_DIFF_2_P
K40 CLK_DIFF_2_N
Figure 1-2.
Table 1-9 shows the FPGA I/O mapping for the SuperClock-2 module
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ADR2 ADR1 ADR0
ON OFF ON
ON OFF OFF
OFF ON ON
OFF ON OFF
OFF OFF ON
OFF OFF OFF
Table 1-7 lists the FPGA pin connections to the
U35 Pin
4
5
Table 1-8.
SMA Connector
J99
J100
J98
J101
VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012