Enable Registers; Queues; Output Queue - Keithley 6517B Reference Manual

Section 13: Status structure

Enable registers

As shown in the illustrations, each status register set has an enable register. An enable register is
programmed by the user and serves as a mask for the corresponding event register. An event bit is
masked when the corresponding bit in the enable register is cleared (0). When masked, a set bit in an
event register cannot set a bit in a following register set or in the status byte register (1 AND 0 = 0).
To use the status byte register to detect events (for example, serial poll), you must unmask the
events by setting (1) the appropriate bits of the enable registers.
The standard event status enable register is programmed and queried using the *ESE and *ESE?
common commands respectively (see
registers are programmed and queried using the :ENABle and :ENABle? commands in the STATus
Subsystem (see
An enable register is not cleared when it is read. The enable registers are affected by the following
operations:

Cycling power: Clears all enable registers

:STATus:PRESet clears the following enable registers:
 Operation event enable register
 Questionable event enable register
Measurement event enable register


:STATus:PRESet sets all bits of the following enable registers:
 Trigger event enable register
 Arm event enable register
 Sequence event enable register

*ESE 0 — Clears the standard event status enable register

Queues

The Model 6517B uses two queues; the output queue and the error queue. The queues are first-in
first-out (FIFO) registers. The output queue is used to hold readings and response messages, and the
error queue is used to hold error messages and status messages. The Model 6517B status model in
Model 6517B status structure
registers.

Output queue

The output queue is used to hold data that pertains to the normal operation of the instrument. For
example, when a query command is sent, the response message is placed in the output queue.
When data is placed in the output queue, the message available (MAV) bit in the status byte register
sets. A data message is cleared from the output queue when it is read. The output queue is
considered cleared when it is empty. An empty output queue clears the MAV bit in the status byte
register.
A message from the output queue is read by addressing the Model 6517B to talk after the appropriate
query is sent.
13-10
Common commands
SCPI command reference
(on page 13-1) shows how the two queues are structured with the other
Model 6517B Electrometer Reference Manual
(on page 12-1)). All other enable
(on page 14-1)).
6517B-901-01 Rev. C / August 2015