Table of Contents
Advertisement
Figure 11–13 VIC Error Group Interrupt Vector Base Register
VME_IF_BASE + 58 :
VIC_EGVIBR
User Programmable Vector-Base
000 ACFail
001 Write Post Fail
010 Arb. Timeout
011 SYSFAIL
100 VMEbus IACK Received
110 DMA Completion
11.1.4 SIO Chip Programmable Interrupt Controller
The 82378 chip is used to deliver interrupts from the mouse, keyboard, and Super
I/O chip (37C665) to the interrupt/mask register.
For programming details of the 8259, see the SIO chip (82378ZB) and 8259 data
sheets.
11.1.4.1 Nonmaskable System Events
In addition to the Nbus device interupts, the SIO chip also sends a nonmaskable
interrupt (NMI) to CPU IRQ line 0.
The front panel HALT button, the watchdog HALT, and a PCI SERR are the
only such nonmaskable events. The two categories of Digital Alpha VME 4
nonmaskable events (halt and SERR) are handled through the SIO chip, which
contains a status register that can be polled to determine the NMI reason. This
register is the NMI status and control register at PCI I/O address 0x00000061.
All NMI events should cause a jump to the console entry point without destroying
the software context, and SERR should report an error. If the interrupt reason
is a HALT, the firmware should also read the reset reason register (PCI I/O
0x80A) to see if the watchdog bit is set. If set, the HALT must be treated as a
''save-software-context'' watchdog HALT.
The nonmaskable description refers to the processor's operation. PALcode
never masks the NMI input pin and the events are considered highest priority.
However, the SIO chip, by default, disables the generation of the interrupt to
the processor so they must be enabled by initialization code. Also, firmware can
operate in ''HALT-protected'' space by disabling the NMI delivery either at the
HIER or SIO chip level.
31
Don't Care
08 07 06 05 04 03 02 01 00
ML013312
System Interrupts 11–11
Advertisement
Table of Contents
Troubleshooting
