Configuration Register For Banks 0 And 1 . . . . . . . . . . 6-7 Timing Register A - DEC Digital Alpha VME 4/224 User Manual

Table 6–6 Configuration Register for Banks 0 and 1
1
Field Name Type
<15:9> Reserved MBZ
<8:6> S0_COLSEL RW
<5> S0_SUBENA RW, 0
1
Field names are for Bank 0.
Description
—
Column address selection. Indicates the number of
valid column bits expected at the DRAMs. Used with
memory width information to generate row or column
addresses. Memory interface width is set at 128 bits.
The field codes for S0_COLSEL<2:0> are:
S0_COLSEL<2:0> Row, Column Bits
000 12, 12
001 12, 10 or 11, 11
010 Reserved
011 10, 10
1XX Reserved
Enables subbanks, defined by S0_SIZE. When clear,
subbanks are disabled and the <3:0>_rasb0_l pins are
asserted only during refreshes.
Cache and Memory Subsystem 6–23
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