Interval Timing Registers - DEC Digital Alpha VME 4/224 User Manual

Table 9–14 (Cont.) TOY Clock Command Register
Field Name
<2>
<3> Watchdog Timer
Enable
<4> Pulse/Level O/P
<5> Watchdog Timer
Assertion
<6> Watchdog Timer
Select
<7> Transfer Enable
The 1024 Hz square wave clock output of the TOY clock is fed to interrupt
register 2<5>. Everytime the clock makes a low-to-high transition, the interrupt
register 2<5> is asserted and held asserted. The interrupt request input is only
deasserted by writing to the heartbeat (clear-interrupt) register at address 0x80C
on the Nbus.

9.7 Interval Timing Registers

CPU Address: 0x1C0080000 - 0x1C00BFFE0
Nbus offset: 0x4000 - 0x7FFF
Digital Alpha VME 4's timer/counters are based on the 82C54 device. For more
detail on the 82C54, see the vendor/DECchip specification.
The 82C54 is made up of three independent but identical 16-bit counter/timers,
implemented by some register/interrupt logic. The programming interface is
bytewide in the Nbus region of PCI I/O space.
On power-up, the chip is in an undefined state and must be initialized before use.
The timer interface takes up the least significant byte of six adjacent longwords
in Nbus space (see Table 9–15). The first four are the standard four bytewide
registers of the 82C54 chip, and the other two bytes are an interrupt status
register.
Type Description
Not used
R/W
R/W
R/W
R/W
R/W Enables/disables changes to the values in the
timekeeping registers. When clear, the current
value in the readable registers is frozen even
though the internal timing continues. This
prevents the update of the registers from
changing the values during a read operation
or from updating the new value during a write
operation.
Nbus 9–25