Module Display Control Register - DEC Digital Alpha VME 4/224 User Manual

Register
Module display control
Module configuration
Interrupt register 1
Interrupt register 2
Interrupt register 3
Interrupt register 4
Memory configuration 0
Memory configuration 1
Memory configuration 2
Memory configuration 3
Reset reason 1
Memory identification
Heartbeat (clear-interrupt)
Module control
Reset reason 2
Bcache configuration
Reset reason 3

9.2.1 Module Display Control Register

CPU address: 0x1C0010000
Nbus offset: 0x800
The display is a 5x7 dot-matrix intelligent display device, with 96 characters. The
unit is read/writable by the display control register (MOD_DISP_REG), shown in
Figure 9–3.
CPU Address
1 C001 0000
1 C001 0020
1 C001 0040
1 C001 0060
1 C001 0080
1 C001 00A0
1 C001 00C0
1 C001 00E0
1 C001 0100
1 C001 0120
1 C001 0140
1 C001 0160
1 C001 0180
1 C001 01A0
1 C001 01C0
1 C001 01E0
1 C001 05C0
Nbus Offset
800
801
802
803
804
805
806
807
808
809
80A
80B
80C
80D
80E
80F
82E
Nbus 9–5