DEC Digital Alpha VME 4/224 User Manual page 103

NCR 53C810 PCI-SCSI I/O Processor Tests
NCR810 Command/Status Register Test
This test writes, reads, and compares all of the NCR810 command/status registers
that are feasible to test. When the test finishes, it returns the registers to their
initialized values.
Console Command: ncr810_diag -t 3
Command Option:
-lp: loop on write/read if the -lp option is specified.
NCR810 Command/Status Register Reset Value Test
This test checks that a reset of the NCR810 sets the command/status registers to
their default values as defined by the NCR810 53C810 chip specification.
Console Command: ncr810_diag -t 4
NCR810 Internal Loopback Test
This test performs a SCSI loopback internal to the NCR810 chip. The following
data patterns are used: all 1s, all 0s, alternating 1s and 0s. The test also verifies
parity checking and that the SCSI reset control lines can be toggled internally.
Console Command: ncr810_diag -t 5
NCR810 Internal Live Bus Loopback Test
This test performs an internal SCSI loopback that also drives the signal lines on
the SCSI bus.
All devices must be removed from the SCSI bus before running this test. Devices
on the bus interfere with the test and cause false error reports. Also, the test
data may produce illegal device instructions and cause the devices to hang.
First the SCSI bus is placed in a high impedance state by loading a data pattern
that causes the output drivers to draw no current. Then the output latches are
checked for the correct data. The test also verifies parity checking and that the
SCSI reset control lines can be toggled internally. The following data patterns are
used: all 1s, all 0s, alternating 1s and 0s.
Console Command: ncr810_diag -t 6
Diagnostics 4–25