Timer Interrupt Status Registers; Timer Interrupt Status Register - DEC Digital Alpha VME 4/224 User Manual

The Timer IRQ line is asserted for a low-to-high transition of a timer's output pin
when that timer is enabled in the CSR to cause an interrupt. The interrupt is
held asserted until the timer status summary register is read (clear on read). The
corresponding timer expiration status bit is always set by a low-to-high on the
timer output but this only causes the IRQ line to be asserted if the corresponding
interrupt enable bit is set.
In addition, the output of timer #1 is brought to the VIC IRQ <3>. As this is
the straight output from the 82C54 chip, the VIC should be programmed for an
edge-sensitive input for this interrupt (all other interrupts in the system are
level).

9.7.5 Timer Interrupt Status Registers

The timer interrupt status register is aliased as the bottom byte in two contiguous
longwords (as shown in Table 9–15). The action of the register is slightly
different, depending on the address at which it is accessed and whether the
access is a read or a write. Figure 9–16 shows the timer interrupt status
register.
Figure 9–16 Timer Interrupt Status Register
TOY_BASE_ADDR + 10/14 :
Timer #2 IRQ Enable
Timer #0 IRQ Enable
Timer #2 Status
Timer #0 Status
Table 9–18 Timer Interrupt Status Register
Field Name
<0>
9–32 Nbus
31
Don't Care
Type Description
Timer #0 status
When clear, the IRQ is dismissed. The bit
is cleared at the end of the read cycle of a
read operation originating from TMR_BASE_
ADDR+14. A read operation from TMR_BASE_
ADDR+10 has no effect.
08 07 06 05 04 03 02 01 00
ML013298
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