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7.1.2 Buffering System Bus Transactions
Write-and-run I/O write transactions use a 1-entry write buffer. One I/O read
transaction is initiated by the CPU. The I/O read buffer is a temporary buffer and
is invalidated at the end of each I/O read transaction.
To function correctly, the CPU must be configured in wrap mode. The PCI host
bridge supports wrapped mode only on transactions initiated by the CPU. The
requested quadword is the only one that is returned on I/O read transactions.
7.1.3 Burst Length and Prefetching for the System Bus
On write transactions directed toward main memory, the PCI host bridge
supports a maximum burst length of 16 longwords. For the maximum burst, the
write transaction must start on an even cache-line boundary with PCI ad<5> =
0 and PCI ad<4:2> = 0. The transaction is terminated using a PCI disconnect
after the sixteenth longword has been received. In all other cases, the burst is
less than 16 longwords.
On CPU-initiated write transactions, a maximum burst length of two is supported
in sparse memory and I/O spaces, and a maximum burst length of eight is
supported in dense memory space.
On CPU-initiated read transactions, a maximum burst length of two is supported.
7.2 Interface to the PCI bus
7.2.1 Decoding PCI Addresses
When an entry in the DMA write buffer is unloaded, the PCI host bridge
translates the 32-bit PCI address into a 34-bit physical address, using either
direct or scatter-gather mapping. The PCI host bridge provides two windows that
are mapped to regions within the PCI address space. In a program, each address
region can be mapped by either method, independently of each other.
7.2.2 Buffering PCI Transactions
The DMA write buffer consists of four entries. Each entry contains the cache-line
address, eight longwords of data, the byte enables for each longword, and a valid
bit for the entry.
The DMA read buffer stores up to 16 longwords of data organized as two cache
lines. A valid bit is implemented with each longword. When data is loaded into
the DMA read buffer, the data's valid bit is set. The PCI host bridge then unloads
the data.
PCI Host Bridge 7–3
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