DEC Digital Alpha VME 4/224 User Manual page 439

show led command, 13–94
show map command, 13–95
show_log command, 13–96
Signal, iogrant, 7–6
Single mode data transfers, 10–7
SIO chip
See Super I/O chip
sleep command, 13–98
Slots, needed for installation, 2–6
Software retriggerable one-shot mode (0),
9–29
sort command, 13–99
sp command, 13–100
SROM, 9–17
initialization countdown, 4–4
tests, 2–27
start command, 13–101
Status
display, 3–2
monitoring, 12–13
Status/error interrupts, 11–8
stop command, 13–102
Subsystems
cache and memory, 6–1
components of, 6–1
I/O, interface to, 8–1
Super I/O chip, 9–18
address space of, 9–2
integrated device electronics (IDE)
register addresses, 9–21
interrupt controller, 11–11
nonmaskable system events, 11–11
register address space of, 9–19
serial port channels, 9–18
Swap modes, 10–26
Switch settings for Digital Alpha VME 4
other, 2–10
system controller, 2–9
Synchronization, PCI and CPU, 7–5
SYSCLK, 10–21
SYSFAIL* assertion, 11–8
System bus, 6–1
address map of, 5–1
address space, 5–3
addresses, decoding of, 6–4
System bus (cont'd)
arbitration on, 6–4
buffering transactions of, 7–3
controller, 6–1, 6–4
error address register, 7–14
interface of, 6–4
interface to, 7–2
System clock, 10–17, 10–21
System module, installing, 2–14
System, getting information about, 12–5
T
Tag enable register, 6–16
Terminals, connecting, 2–21
TFTP, 13–6
TGA_SYNC_GREEN environment
variable, 3–6
Time-of-year (TOY) clock
See TOY clock
Timeout
PCI bus master, 7–7
PCI host bridge retry, 7–7
Timeout timers, 10–17, 10–21
Timeouts, arbitration, 11–8
Timer
interface registers, 9–25
interrupt status registers, 9–32
modes, 9–29
registers, 9–28
Timer 0, 9–28, 9–29
exercising, 4–11, 4–12
loopback test, 4–12
Timer 1, 9–28, 9–29
exercising, 4–11
interrupt test, 4–14
verifying the interrut path of, 4–14
Timer 2, 9–28, 9–29
exercising, 4–10, 4–11
interrupt test, 4–13
square wave test, 4–11
terminal count test, 4–10
Timers, 1–2, 9–25
diagnostic tests for, 4–4
local bus transfer, 10–23
Index–15