Watchdog Timer - DEC Digital Alpha VME 4/224 User Manual

Table 9–18 (Cont.) Timer Interrupt Status Register
Field Name
<1>
<2:3> Not used
<4>
<5>
Bits <1:0> dismiss the interrupt according to the following combination:
IRQ = (BIT <0> and BIT <4>) or (BIT <1> and BIT <5>)
Bits <5:4> are not writable. However, a write operation to address TMR_BASE_
ADDR+10 toggles bit <4> only and a write operation to TMR_BASE_ADDR+14
toggles bit <5> only. All other bits in the register are unaffected.

9.8 Watchdog Timer

The watchdog timer is included to allow hardware to bring the system back to
some known state when software fails to function correctly. This timer is located
on the same chip as the TOY clock.
The watchdog timer is initialized with some time value (in the range 0.01 to 99.9
seconds). If left unaccessed, the timer decrements towards 0. If allowed to reach
0, the watchdog timer first halts the system (jump to Halt entry firmware) and
then forces the module into hardware reset (some 300 ms later). The module
can be maintained by periodically accessing the watchdog timer registers. Any
access to these registers resets the time back to the initialized value. Therefore,
as long as the worst-case time between watchdog timer access is less than the
programmed timeout value, the module functions normally.
In addition to the hardware support for the watchdog timer operation, console
firmware can be configured to dispatch to user code or continue with its default
reset action on watchdog timer timeout. Firmware can detect the expiration
of the watchdog timer during reset code by examining the hardware reset
reason register (see Section 9.2.5). The ''jump to halt'' code just before causing
a hardware reset enables firmware to take a snap-shot of the processor state
Type Description
Timer #2 status
When clear, the IRQ is dismissed. The bit
is cleared at the end of the read cycle of a
read operation originating from TMR_BASE_
ADDR+14. A read operation from TMR_BASE_
ADDR+10 has no effect.
Read Status of Timer #0 IRQ Enable. When set, the
timer output line has made an active transition.
Read Status of Timer #2 IRQ Enable. When set, the
timer output line has made an active transition.
Nbus 9–33