DEC Digital Alpha VME 4/224 User Manual page 176

Table 7–2 (Cont.) Diagnostic Control/Status Register
Field Name
<14> IPTL
<13> UMRD
<12> CMRD
<11> NDEV
<10> TABT
<9> IOPE
<8> DDPE
<7> Reserved
7–12 PCI Host Bridge
Type Description
RWC, 0 Invalidate page table lookup. This bit is set when
the longword scatter-gather map entry being
accessed is invalid. Bits ad<31:0> are logged in
the PCI error address register, if it is not already
locked.
RWC, 0 Uncorrectable memory read data. This bit is set
when an uncorrectable error is encountered by the
21071-DA chip in the data read from the DMA read
buffer in the 21071-BA chip to the 21071-DA chip
on a DMA read or a scatter-gather read transaction.
Bits sysadr<33:6> are logged in system bus error
address register bits <31:4> if it is not locked.
RWC, 0 Correctable memory read data (CMRD) is set when
a correctable error is encountered by the 21071-DA
chip. The error is encountered when the data read
from the DMA read buffer in the 21071-BA reaches
the 21071-DA on a DMA read or scatter-gather read
transaction.
RWC, 0 No device. This bit is set when devsel# signal is
not asserted in response to an I/O read or write
transaction initiated on the PCI by the 21071-DA.
Bits ad<31:0> are logged in the PCI error address
register.
RWC, 0 Target abort. This bit is set when a PCI slave device
ends an I/O read or write transaction using the PCI
target abort protocol. Bits ad<31:0> are logged in
the PCI error address register.
RWC, 0 I/O parity error. This bit is set when a parity error
occurs in the data phase of an I/O read or write
transaction. Bits ad<31:0> are logged in the PCI
error address register.
RWC, 0 DMA data parity error. This bit is set when a parity
error occurs in the data phase of a DMA transaction.
Bits ad<31:0> for this transaction are logged in the
PCI error address register.
MBZ —
(continued on next page)