Pci Configuration Space (0X1E0000000 To 0X1Ffffffff); Pci Configuration Space Definition - DEC Digital Alpha VME 4/224 User Manual

5.1.7 PCI Configuration Space (0x1E0000000 to 0x1FFFFFFFF)
A read or write access to this space causes a configuration read or write cycle on
the PCI. There are two classes of targets: devices on the primary PCI bus and
devices on the secondary PCI buses that are accessed through PCI-to-PCI bridge
chips.
During PCI configuration cycles, the meanings of the address fields vary
depending on the intended target of the configuration cycle. Bits ad<1:0>,
which are supplied by the HAXR2 register, indicate the target bus:
Bits ad<1:0> equal to 00 indicate the primary PCI bus.
Bits ad<1:0> equal to 01 indicate a secondary PCI bus.
Table 5–3 defines the various fields of PCI ad<31:0> during the address phase of
a configuration read or write cycle.
Table 5–3 PCI Configuration Space Definition
Target Bus
Primary PCI Bus
Secondary PCI Buses
(Must pass through a PCI-to-PCI bridge)
Table 5–4 translates bits sysAdr<20:16> to PCI primary bus addresses.
5–8 System Address Mapping
ad Bits Definition
<31:11> Decoded from sysAdr<20:16> according to
Table 5–4.
Can be used for IDSEL# or don't care states.
Typically, the IDSEL# pin of each device is
connected to a unique ad line.
<10:8> Function select (1 of 8) from sysAdr<15:13>
<7:2> Register select from sysAdr<12:7>
<1:0> 00 from HAXR2<1:0>
<31:24> Forced to 0 by the 21071-DA chip
<23:16> Secondary bus number from sysAdr<28:21>
<15:11> Device number from sysAdr<20:16>
<10:8> Function select (1 of 8) from sysAdr<15:13>
<7:2> Register select from sysAdr<12:7>
<1:0> 01 from HAXR2<1:0>