Super I/O Chip; Serial Port Channels A And B; Flash Rom Layout/Addressing - DEC Digital Alpha VME 4/224 User Manual

Figure 9–11 Flash ROM Layout/Addressing
ROM_BASE_ADDR :
The flash ROM can be rewritten. To protect the flash ROM from unauthorized
/accidental updates, a hardware switch must be closed before write operations
are enabled. The switch, DIP switch 2 on the Digital Alpha VME 4 assembly,
must always be open unless flash ROM is going to be updated. The state of
the switch is stored in the Flash Switch bit <3> of the module control register.
The flash ROM is also protected by a software enable; the Flash Write Enable
bit <2> and the Flash Switch bit <3> of the module control register must be
set to enable flash updates.

9.4 Super I/O Chip

The FDC37C665GT Super I/O (SIO) chip supports two 16550 UARTS (channel
A and channel B) and one parallel port. It provides FIFO for serial ports and
EPP/ECP modes for the parallel port.
For more information on the SIO chip and its operation, see SMC's
FDC37C665GT Super I/O Specification.

9.4.1 Serial Port Channels A and B

The SIO chip supports channels A and B. Channel A is used for the Digital Alpha
VME 4 console. It is configured by firmware as an asynchronous line. You can
define the configuration by setting the baud rate, parity, data bits, and stop bit
values that are stored in NVRAM.
In the absence of valid data in NVRAM on power-up, channel A is programmed
with a default of 9600 baud, 8-bits, no parity, and one stop bit.
9–18 Nbus
<00>
512 KB
512 KB
<01>
1 MB
<10>
1 MB
<11>
1 MB
Start of Console Firmware
Start of User Flash
ML013291