DEC Digital Alpha VME 4/224 User Manual page 91

This test enables only timer 0 as done in test 3 but does not use timer 1 or
timer 2. The clock and gate come from the timers on the master Digital Alpha
VME 4 module. Timer 0 interrupts when the gate is received and its count is
decremented to 0.
A VMEbus P2 loopback connector is required. See Figure 4–1 for a
description of the loopback connections.
Console Command: i8254_diag -t 4
Command Option:
-np: no print option; if specified no P2 connector message is printed
Miscellaneous Note
Test #3 must be invoked, with the -lp option, on the master module prior to
invoking this test.
Timer 2 Interrupt Test
This test exercises timer 2 with the timer interrupt disabled. In the Digital Alpha
VME 4 design, the gate input for timer 2 is always enabled and the clock input is
connected to a 10 MHz (100 ns period) clock source.
Timer 2 is programmed to mode 0, interrupt on terminal count. After the timer is
initially programmed to mode 0 and loaded with a count value, the OUT output is
low and remains low until the internal count value reaches zero. When the count
value reaches zero, OUT output is asserted high and remains high until timer 2
is reprogrammed. The event of OUT transitioning from low to high should set the
timer 2 status bit and not generate a CPU interrupt.
The ISR global flag is checked verifying that the ISR was not invoked. The timer
2 status bit is checked to indicate the interrupt took place.
Console Command: i8254_diag -t 5
Miscellaneous Notes
• The interrupt enable bits for timers 0 and 2 (bits 4 and 5 of the interrupt
status register at address 0x4010) are not directly writable. Bit 4 is toggled
by writing to address 0x4010; bit 5 is toggled by writing to address 0x4014.
In both cases, the data written is Don't Care.
• A read of the interrupt status register at address 0x4014 causes both
interrupt status bits (bits 0 and 1) to be cleared.
Interval Timer Tests
Note
Diagnostics 4–13