System Bus Interface; Arbitration On The System Bus; System Bus Controller; Decoding Addresses - DEC Digital Alpha VME 4/224 User Manual

6.1 System Bus Interface

The CPU, DECchip 21071-CA, PCI host bridge, cache, and memory communicate
with each other through the system bus. The system bus is the processor pin
bus with additional signals for DMA transaction control, arbitration, and cache
control.

6.1.1 Arbitration on the System Bus

The DECchip 21071-CA arbitrates between the CPU and 21071-DA chip when
these components request use of the system bus or the Bcache. The CPU owns
the system bus by default so it has access to the Bcache whenever the 21071-DA
(PCI Host Bridge) is not requesting the system bus.

6.1.2 System Bus Controller

The system bus controller consists of:
• A sequencer that receives CPU and DMA command fields for decode
• Results from the system bus arbiter logic
• Status from the memory controller logic
The sequencer then supplies machine state signals that are used to:
• Generate requests for Bcache control and read to the memory controller
• Load data from the system bus into the read, merge, and write buffers
• Acknowledge cycles to the CPU and 21071-DA chip
The system bus controller supports wrapping on the system bus.

6.1.3 Decoding Addresses

The system bus interface logic decodes the system bus address for both CPU
and DMA requests to determine the action to take. It supports cacheable and
noncacheable memory accesses as well as accesses to its control/status register
(CSR) space.
6–4 Cache and Memory Subsystem