DEC Digital Alpha VME 4/224 User Manual page 440

Timers (cont'd)
VMEbus arbitration, 10–21
VMEbus timeout, 10–21
VMEbus transfer, 10–22
3 timers loopback test, 4–11
Timing register A, 6–25
Timing register B, 6–26
TLB
data registers, 7–21
tag registers, 7–20
TOY clock, 9–22
bitwalk test, 4–20
command register, 9–24
diagnostic tests for, 4–3
register test, 4–3
registers, testing, 4–20
testing, 4–27
time advancement test, 4–21
timekeeping registers, 9–23
Transfer timers, 10–22, 10–23
Translated base registers, 7–15
Translation buffer invalidate all register,
7–22
Troubleshooting, 2–29
TTY_DEV environment variable, 3–6
U
update command, 13–103
V
VERSION environment variable, 3–6
VIC
arbiter/requester configuration register,
10–18
block transfer control register, 10–8
error group interrupt control register,
11–9
error group interrupt vector base
register, 11–10
interrupt request/status register,
10–23
local interrupt vector base register,
11–7
register writer/read test, 4–28
Index–16
VIC (cont'd)
release control register, 10–20
write post failure, 11–8
VIC64 chip, 9–29
byte swapping for, 10–27
configuring, 10–32
interrupt controller, 11–4
interrupt ranking for, 11–5
interrupts
sources of, 11–6
VIP PCI configuration register test, 4–4,
4–28
VIP register write/read test, 4–4, 4–28
vip_diag command
with -t 1, 4–28
with -t 2, 4–28
with -t 3, 4–28
with -t 4, 4–29
VME interface, 10–1
address spaces of, 10–2
addresses, decoding, 10–10
base and mask register, 10–11
block mode data transfers, 10–7
byte swapping, 10–26
VIC64, 10–27
components of, 10–1
configuring VIC64, 10–32
data transfers, 10–7
diagnostic tests for, 4–4
Digital Alpha VME 4
as system controller, 10–17
draft standards for, 10–2
initializing, 10–30
interprocessor communication, 10–14
global switches, 10–14
module switches, 10–15
registers for, 10–14
logic, global reset of, 10–17
master DMA transfer with, 10–9
processor
testing, 4–28
processor page monitor CSR, 10–13
programming scatter-gather RAM,
10–31
purposes of, 10–2