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DEC AlphaPC 164LX Technical Reference Manual

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DIGITAL Semiconductor
AlphaPC 164LX Motherboard
Technical Reference Manual
Order Number: EC–R46WB–TE
Revision/Update Information:
Digital Equipment Corporation
Maynard, Massachusetts
http://www.digital.com/semiconductor
This is a revised, preliminary document. It
supersedes the DIGITAL Semiconductor
AlphaPC 164LX Motherboard Technical
Reference Manual (EC–R46WA–TE).
Preliminary

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  • Page 1 DIGITAL Semiconductor AlphaPC 164LX Motherboard Technical Reference Manual Order Number: EC–R46WB–TE Revision/Update Information: This is a revised, preliminary document. It supersedes the DIGITAL Semiconductor AlphaPC 164LX Motherboard Technical Reference Manual (EC–R46WA–TE). Preliminary Digital Equipment Corporation Maynard, Massachusetts http://www.digital.com/semiconductor...
  • Page 2 January 1998 While DIGITAL believes the information included in this publication is correct as of the date of publication, it is subject to change without notice. Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description.

  • Page 3: Table Of Contents

    2–6 AlphaPC 164LX Connector Pinouts ........
  • Page 4 AlphaPC 164LX Bcache Interface ........
  • Page 5 Upgrading the AlphaPC 164LX Configuring SDRAM Memory ........
  • Page 6 Enclosure ............B–3 Support, Products, and Documentation Index...
  • Page 7 AlphaPC 164LX PCI Bus Devices ........
  • Page 8 AlphaPC 164LX System Interrupts ........
  • Page 9 Scope This manual describes the features, configuration, functional operation, and inter- faces of the AlphaPC 164LX motherboard. This manual does not include specific bus specifications (for example, PCI or ISA buses). Additional information is avail- able in the AlphaPC 164LX schematics, program source files, and the appropriate vendor and IEEE specifications.
  • Page 10 Chapter 1, Introduction, is an overview of the AlphaPC 164LX motherboard, • including its components, features, and uses. Chapter 2, System Configuration and Connectors, describes the user-environ- • ment configuration, board connectors and functions, and jumper functions. It also identifies jumper and connector locations.
  • Page 11 Bit/Field Abbreviation Description RO (read only) Bits and fields specified as RO can be read but not written. RW (read/write) Bits and fields specified as RW can be read and written. WO (write only) Bits and fields specified as WO can be written but not read. •...
  • Page 12 Memory figures have addresses starting at the top and increasing toward the bottom. Schematic References Logic schematics are included in the AlphaPC 164LX design package. In this man- ual, references to schematic pages are printed in italics. For example, the following specifies schematic page 4: “.
  • Page 13 Signal Names All signal names are printed in boldface type. Signal names that originate in an industry-standard specification, such as PCI or IDE, are printed in the case as found in the specification (usually uppercase). Active-high signals are indicated by the _h suffix.
  • Page 14 – An occurrence specified as UNPREDICTABLE may or may not hap- pen based on an arbitrary choice function. The choice function is subject to the same constraints as are UNPREDICTABLE results and must not constitute a security hole. Specifically, UNPREDICTABLE results must not depend upon, or be a function of, the contents of memory locations or registers that are inaccessible to the current process in the current access mode.

  • Page 15: Introduction

    The board also provides a platform for PCI I/O device hardware and software devel- opment. 1.1 System Components and Features The AlphaPC 164LX is implemented in industry-standard parts and uses a DIGITAL Semiconductor Alpha 21164 microprocessor running at 466, 533, and 600 MHz. Figure 1–1 shows the board’s functional components.

  • Page 16: Alphapc 164Lx Functional Block Diagram

    System Components and Features Figure 1–1 AlphaPC 164LX Functional Block Diagram Index Control Alpha 21164 Microprocessor 2MB L3 Bcache Bcache Tag Data 128-Bit Data Quick Switches Check (X16) 168-Pin Unbuffered Control SDRAM DIMM Sockets Address (X4) DECchip 21174-CA Control, I/O Interface,...

  • Page 17: Alphapc 164Lx Sdram Memory Configurations

    100 MHz or faster speed. Two DIMMs provide 32Mb to 256MB of memory, while four DIMMs provide up to 512MB. Table 1–1 lists the DIMM sizes tested and the corresponding main memory size for 128-bit arrays. Table 1–1 AlphaPC 164LX SDRAM Memory Configurations Total Memory...

  • Page 18: L3 Bcache Subsystem Overview

    Bcache. 1.1.4 PCI Interface Overview The AlphaPC 164LX PCI interface is the main I/O bus for the majority of functions (SCSI interface, graphics accelerator, and so on). The PCI interface has a 33-MHz data transfer rate. PCI-IDE support is provided by an onboard controller chip (CMD646).

  • Page 19: Software Support

    Windows NT operating system. The AlphaBIOS firmware resides in the flash ROM on the 21A04-C0 variation of the AlphaPC 164LX motherboard. Binary images of the AlphaBIOS firm- ware are included in the motherboard Software Developer’s Kit (SDK), along with a license describing the terms for use and distribution.

  • Page 20: Motherboard Software Developer's Kit (Sdk)

    The Alpha Motherboard Debug Monitor firmware with source code. • Power-up initialization SROM and SROM Mini-Debugger with source code. • Sample PALcode sources modeled after DIGITAL UNIX with source code. • Fail-safe booter with source code. • Various additional tools with source code.

  • Page 21: System Configuration And Connectors

    This chapter describes the AlphaPC 164LX configuration, board connectors and functions, and jumper functions. It also identifies jumper and connector locations. The AlphaPC 164LX uses jumpers to implement configuration parameters such as system speed and boot parameters. These jumpers must be configured for the user’s environment.

  • Page 22: Alphapc 164Lx Jumper/Connector/Component Location

    Figure 2–1 AlphaPC 164LX Jumper/Connector/Component Location Top: Mouse Top: COM1 Bottom: Bottom: Denotes Pin #1 Keyboard COM2 FM-05933.AI4 22 January 1998 – Subject To Change System Configuration and Connectors 2–2...

  • Page 23: Alphapc 164Lx Jumper/Connector/Component List

    Table 2–1 AlphaPC 164LX Jumper/Connector/Component List Item Description Item No. Description RTC battery (CR2032) Hard-drive LED connector Soft power connector PCI slot 0 (64-bit) Fan power, enclosure (+12V) System configuration jumpers Power (+3V, +5V, -5V, +12V, -12V) Flash ROM update enable/disable...

  • Page 24: Alphapc 164Lx Configuration Jumpers

    AlphaPC 164LX Configuration Jumpers 2.1 AlphaPC 164LX Configuration Jumpers The AlphaPC 164LX motherboard has two groups of jumpers located at J27 and J28, as shown previously in Figure 2–1. These jumpers set the hardware configuration and boot options. Figure 2–2 shows the jumper functions for each group.

  • Page 25: Cpu Speed Selection

    The Bcache size jumpers are located at J27–11/12 (CF1) and J27–13/14 (CF2), as shown in Figure 2–2. The AlphaPC 164LX is configured with 2MB of Bcache during production; the other jumpers shown in Figure 2–2 (0, 1, and 4) are for other implementations.

  • Page 26: Flash Rom Update Jumper (J28)

    When J28–2/3 are jumpered together (default), the flash ROM is write-enabled. When J28–1/2 are jumpered together, the flash ROM is write-protected. 2.7 AlphaPC 164LX Connector Pinouts This section lists the pinouts of all AlphaPC 164LX connectors. See Figure 2–1 for connector locations. 2.7.1 PCI Bus Connector Pinouts Table 2–2 shows the PCI bus connector pinouts.
  • Page 27 AlphaPC 164LX Connector Pinouts Table 2–2 PCI Bus Connector Pinouts (Sheet 2 of 2) Signal Signal Signal Signal AD<23> AD<21> AD<19> AD<17> C/BE#<2> IRDY# DEVSEL# LOCK# PERR# SERR# C/BE#<1> AD<14> AD<12> AD<10> Not used Not used AD<08> AD<07> AD<05> AD<03>...

  • Page 28: Isa Expansion Bus Connector Pinouts

    AlphaPC 164LX Connector Pinouts 2.7.2 ISA Expansion Bus Connector Pinouts Table 2–3 shows the ISA expansion bus connector pinouts. Table 2–3 ISA Expansion Bus Connector Pinouts (J30, J31) Signal Signal Signal Signal IOCHCK# RSTDRV IRQ9 –5V DRQ2 –12V ZEROWS# +12V...

  • Page 29: Sdram Dimm Connector Pinouts

    AlphaPC 164LX Connector Pinouts 2.7.3 SDRAM DIMM Connector Pinouts Table 2–4 shows the SDRAM DIMM connector pinouts. Table 2–4 SDRAM DIMM Connector Pinouts (J8 through J11) (Sheet 1 of 2) Signal Signal Signal Signal DQ10 DQ11 DQ12 DQ13 DQ14 DQ15...

  • Page 30: Eide Drive Bus Connector Pinouts

    Pins 1 through 84 are on the front side and pins 85 through 168 are on the back side. The AlphaPC 164LX uses BA1 as both BA1 and ADDR12. Therefore, four-bank DIMMs using ADDR<11:0> are the maximum size. (Two-bank DIMMs can use ADDR<12:0>.) Pull-down.

  • Page 31: Diskette Drive Bus Connector Pinouts

    AlphaPC 164LX Connector Pinouts 2.7.5 Diskette Drive Bus Connector Pinouts Table 2–6 shows the diskette (floppy) drive bus connector pinouts. Table 2–6 Diskette (Floppy) Drive Bus Connector Pinouts (J15) Signal Signal Signal Signal DEN0 DEN1 INDEX MTR0 MTR1 STEP WDATA...

  • Page 32: Com1/Com2 Serial Line Connector Pinouts

    AlphaPC 164LX Connector Pinouts 2.7.7 COM1/COM2 Serial Line Connector Pinouts Table 2–8 shows the COM1/COM2 serial line connector pinouts. Table 2–8 COM1/COM2 Serial Line Connector Pinouts (J4) COM1 Pin COM2 Pin (Top) COM1 Signal (Bottom) COM2 Signal DCD1 DCD2 RxD1...

  • Page 33: Srom Test Data Input Connector Pinouts

    AlphaPC 164LX Connector Pinouts 2.7.9 SROM Test Data Input Connector Pinouts Table 2–10 shows the SROM test data input connector pinouts. Table 2–10 SROM Test Data Input Connector Pinouts (J29) Signal Name — SROM_CLK_L Clock out — — TEST_SROM_D_L SROM serial data in —...

  • Page 34: Microprocessor Fan Power Connector Pinouts

    AlphaPC 164LX Connector Pinouts 2.7.12 Speaker Connector Pinouts Table 2–13 shows the speaker connector pinouts. Table 2–13 Speaker Connector Pinouts (J20) Signal Name SPKR Speaker output — — — 2.7.13 Microprocessor Fan Power Connector Pinouts Table 2–14 shows the microprocessor fan power connector pinouts.

  • Page 35: Ide Drive Led Connector Pinouts

    AlphaPC 164LX Connector Pinouts 2.7.15 IDE Drive LED Connector Pinouts Table 2–16 shows the IDE drive LED connector pinouts. Table 2–16 IDE Drive LED Connector Pinouts (J25) Signal Name HD_ACT_L Hard drive active HD_LED_L Hard drive LED input 2.7.16 Reset Button Connector Pinouts Table 2–17 shows the reset button connector pinouts.

  • Page 37: Power And Environmental Requirements

    3.1 Power Requirements The AlphaPC 164LX derives its main dc power from a user-supplied power supply. The board has a total power dissipation of 100 W, excluding any plug-in PCI and ISA devices. An onboard +5-V to +2.5-V dc-to-dc converter is designed to handle 24 A of current.

  • Page 38: Environmental Requirements

    The 21164 microprocessor is cooled by a small fan blowing directly into the chip’s heat sink. The AlphaPC 164LX motherboard is designed to run efficiently by using only this fan. Additional fans may be necessary depending upon cabinetry and the requirements of plug-in cards.

  • Page 39: Atx Hole Specification

    Board Dimensions 3.3.1 ATX Hole Specification Figure 3–1 shows the ATX hole specification for the AlphaPC 164LX. Figure 3–1 ATX Hole Specification .800 TYP Between Connectors 4.900 .650 .500 1.612 .400 1.300 .600 PCI Connector .625 (4 Places) 8.950 6.100 9.600...

  • Page 40: Atx I/O Shield Requirements

    Board Dimensions 3.3.2 ATX I/O Shield Requirements Figure 3–2 shows the ATX I/O shield dimensions for the AlphaPC 164LX. Figure 3–2 ATX I/O Shield Dimensions R 1.00 21.36 16.05 5.00 TYP 9.25 3.58 2.45 4.35 11.15 15.47 14.96 17.95 22.95 23.96...

  • Page 41: Functional Description

    Functional Description This chapter describes the functional operation of the AlphaPC 164LX. The descrip- tion introduces the DIGITAL Semiconductor 21174 core logic chip and describes its implementation with the 21164 microprocessor, its supporting memory, and I/O devices. Figure 1–1 shows the AlphaPC 164LX major functional components.

  • Page 42: Alphapc 164Lx Bcache Interface

    The 21164 microprocessor controls the board-level L3 backup cache (Bcache) array (see Figure 4–1). The data bus (data_h<127:0>), check bus (data_check_h<15:0>), tag_dirty_h, and tag_ctl_par_h signals are shared with the system interface. Figure 4–1 AlphaPC 164LX L3 Bcache Array Bcache 21164 index_h<21:4>...

  • Page 43: Digital Semiconductor 21174 Core Logic Chip

    PCI I/O interface, and includes the DIGITAL Semiconductor 21174-CA chip packaged in a 474-pin plastic ball grid array (PBGA). Figure 4–2 shows the AlphaPC 164LX implementation of the 21174 core logic chip. Figure 4–2 Main Memory Interface...

  • Page 44: 21174 Chip Overview

    Sixteen Quick Switches provide the interface between the 21164/L3 cache (data_h<127:0>, check_h<15:0>) and the memory/21174 (mem_data_h<127:0>, mem_check_h<15:0>). The AlphaPC 164LX supports four 168-pin unbuffered 72-bit SDRAM DIMM modules. Quadword ECC is supported on the SDRAM and CPU buses. Even parity is generated on the PCI bus.

  • Page 45: Alphapc 164Lx Pci Bus Devices

    Semiconductor 21174 Core Logic Chip Technical Reference Manual. 4.2.3 PCI Devices The AlphaPC 164LX uses the PCI bus as the main I/O bus for the majority of periph- eral functions. As Figure 4–3 shows, the board implements the ISA bus as an expan- sion bus for system support functions and for relatively slow peripheral devices.

  • Page 46: Saturn-Io (Sio) Chip

    DIGITAL Semiconductor 21174 Core Logic Chip the configuration and operating frequencies, the PCI bus supports up to 264-MB/s (33 MHz, 64-bit) peak throughput. The PCI provides parity on address and data cycles. Three physical address spaces are supported: • 32-bit memory space •...

  • Page 47: Pci Expansion Slots

    ISA Bus Devices 4.2.5 PCI Expansion Slots Four dedicated PCI expansion slots are provided on the AlphaPC 164LX. This allows the system user to add additional 32-bit or 64-bit PCI options. While both the 32-bit and the 64-bit slots use the standard 5-V PCI connector and pinout, +3.3 V is supplied for those boards that require it.

  • Page 48: Alphapc 164Lx Isa Bus Devices

    Time-of-year clock–A DS1287-compatible clock is backed up by a replaceable battery. An onboard clock generator chip supplies a 14.3-MHz reference clock for the dis- kette data separator and serial ports. Figure 4–4 AlphaPC 164LX ISA Bus Devices PCI Bus ISA1 ISA0 PCI-to-ISA la<23:17>...

  • Page 49: Utility Bus Memory Device

    ISA Bus Devices 4.3.2 Utility Bus Memory Device The AlphaPC 164LX Ubus drives a flash ROM memory device. The flash ROM chip provides 1MB of flash memory for operating system support. Flash data is accessed through 20 address inputs. The low-order 19 address bits are driven by ISA bus sa<18:0>.

  • Page 50: Flash Rom Address Map

    SIO. However, the AlphaPC 164LX system has more external interrupts than the SIO can handle. Therefore, all the ISA interrupts are sent to the SIO except for the two 21174 interrupts, the TOY interrupt, the IDE controller interrupt, and the 16 PCI interrupts.

  • Page 51: Interrupt Logic

    Interrupts Figure 4–5 Interrupt Logic 22 January 1998 – Subject To Change Functional Description 4–11...

  • Page 52: Alphapc 164Lx System Interrupts

    Interrupts Table 4–2 AlphaPC 164LX System Interrupts 21164 Interrupt Suggested Usage AlphaPC 164LX Usage cpu_irq<0> Corrected system error Corrected ECC error and sparse space reserved encod- ings detected by the 21174 cpu_irq<1> — PCI and ISA interrupts cpu_irq<2> Interprocessor and...

  • Page 53: Isa Interrupts

    Interrupts Table 4–3 ISA Interrupts Interrupt Number Interrupt Source IRQ0 Internal timer IRQ1 Keyboard IRQ2 Interrupt from controller 2 IRQ3 COM2 IRQ4 COM1 IRQ5 Available IRQ6 Diskette (floppy) IRQ7 Parallel port IRQ8# Reserved IRQ9 Available IRQ10 Available IRQ11 Available IRQ12 Mouse IRQ13 Available...

  • Page 54: Interrupt Pld Function

    Interrupts 4.4.1 Interrupt PLD Function The MACH210A PLD is an 8-bit I/O slave on the ISA bus at hex addresses 804, 805, and 806. This is accomplished by a decode of the three ISA address bits sa<2:0> and the three ecas_addr<2:0> bits. Each interrupt can be individually masked by setting the appropriate bit in the mask register (see Figure 4–6).

  • Page 55: System Clocks

    4.5 System Clocks Figure 4–7 shows the AlphaPC 164LX clock generation and distribution scheme. The AlphaPC 164LX system includes input clocks to the microprocessor as well as clock distribution for the various system memory and I/O devices. There are other miscellaneous clocks for ISA bus support.

  • Page 56: Alphapc 164Lx System Clocks

    System Clocks Figure 4–7 AlphaPC 164LX System Clocks clk_in_h Microprocessor 21164 Clock Microprocessor Synthesizer clk_in_l (MC12439) pc164lx.3 irq_h<3:0> J27 Jumpers CY2308 pc164lx.2 sys_clk_out1 21174 DIMM0 dram_clkax2 DIMM1 dram_clkbx2 DIMM2 dram_clkcx2 DIMM3 dram_clkdx2 pciclk_slot0 pciclk_slot1 pciclk_slot2 pciclk_slot3 Slots pciclk_ide pc164lx.20-21 pciclk_arb...

  • Page 57: Reset And Initialization

    Reset and Initialization At system reset, the 21164 microprocessor’s irq_h<3:0> pins are driven by the clock divisor values set by four jumpers on J27. During normal operation, these sig- nals are used for interrupt requests. The pins are either switched to ground or pulled up in a specific combination to set the 21164 microprocessor’s internal divider.

  • Page 58: Serial Rom

    Serial ROM Figure 4–8 System Reset and Initialization pc164lx.31 Power Sense shdn_l To +2.5-V Regulator +3 V pc164lx.32 pc164lx.28 21174 pc164lx.7 fan_ok_l pc164lx.22 Fan Sensor rst_l System pc164lx.30 pc164lx.28 Reset sys_reset(n)_l Buffering Debounce irq_reset_l IRQ Mux sys_reset_l 21164 b_dcok dc_ok_h Reset Switch pc164lx.30 pc164lx.29...

  • Page 59: Dc Power Distribution

    FM-05952.AI4 4.8 DC Power Distribution The AlphaPC 164LX derives its system power from a user-supplied PC power sup- ply. The power supply must provide +12 V dc and -12 V dc, -5 V dc, +3 V dc, and +5 V dc (Vdd). The dc power is supplied through power connector J3 (pc164lx.31), as shown in Figure 4–10.
  • Page 60 DC Power Distribution Vdd (+5.0 V) is supplied to ISA connectors, PCI32 connectors, and most of the board’s integrated circuits. Vdd also drives the +2.5-V regulator, which supplies the 21164 microprocessor. Functional Description 22 January 1998 – Subject To Change 4–20...

  • Page 61: Alphapc 164Lx Power Distribution

    DC Power Distribution Figure 4–10 AlphaPC 164LX Power Distribution 22 January 1998 – Subject To Change Functional Description 4–21...

  • Page 63: Upgrading The Alphapc 164Lx

    For a list of vendors who supply components and accessories for the AlphaPC 164LX, see Appendix B. Refer to Figure 2–1 for DIMM connector locations. 72 is not supported. Note: Table 5–1 AlphaPC 164LX SDRAM Memory Configurations (Sheet 1 of 2) Total Memory Bank 0 (J8 and J9)

  • Page 64: Upgrading Sdram Memory

    16Mb 16Mb 5.2 Upgrading SDRAM Memory You can upgrade memory in the AlphaPC 164LX by adding more DIMMs or replac- ing the ones that you have with a greater size. Use the following general guidelines: 1. Observe antistatic precautions. Handle DIMMs only at the edges to prevent damage.

  • Page 65: Preparatory Information

    Use of antistatic mats, ESD approved workstations, or exercising other good ESD prac- tices is recommended. A DIGITAL Semiconductor 21164 microprocessor with a higher speed rating is available from your local distributor. See Appendix B for information about support- ing products.

  • Page 66: Installing The 21164 Microprocessor

    6. Install the heat sink and heat-sink fan as directed in the following steps. A heat- sink/fan kit is available from the vendor listed in Appendix B. Refer to Figure 5–1 for heat-sink and fan assembly details. Upgrading the AlphaPC 164LX 22 January 1998 – Subject To Change 5–4...

  • Page 67: Fan/Heat-Sink Assembly

    3. Place the GRAFOIL pad on the gold-plated slug surface and align it with the threaded studs. 22 January 1998 – Subject To Change Upgrading the AlphaPC 164LX 5–5...
  • Page 68 4. Plug the fan power/sensor cable into connector J18. When installing the microprocessor, you must change the frequency of Important: its clock output by setting the system clock divisor jumpers, as described in Section 2.2. Upgrading the AlphaPC 164LX 22 January 1998 – Subject To Change 5–6...

  • Page 69: System Address Space

    System Address Space This appendix describes the mapping of 21164 40-bit physical addresses to memory and I/O space addresses. It also describes the translation of a 21164-initiated address (addr_h<39:4>) into a PCI address (ad<63:0>) and the translation of a PCI-initiated address into a physical memory address.

  • Page 70: Physical Address Map (Byte/Word Mode Enabled)

    Address Map Table A–1 Physical Address Map (Byte/Word Mode Disabled) (Sheet 2 of 2) 21164 Address Size (GB) Selection 87.2000.0000 – 87.3FFF.FFFF 0.50 PCI special/interrupt acknowledge 87.4000.0000 – 87.4FFF.FFFF 0.25 21174 main CSRs 87.5000.0000 – 87.5FFF.FFFF 0.25 21174 memory control CSRs 87.6000.0000 –...
  • Page 71 Address Map Table A–2 Physical Address Map (Byte/Word Mode Enabled) (Sheet 2 of 2) 21164 Address Size (GB) Selection 87.6000.0000 – 87.6FFF.FFFF 0.25 21174 PCI address translation 87.7000.0000 – 87.7FFF.FFFF 0.25 Reserved 87.8000.0000 – 87.8FFF.FFFF 0.25 21174 miscellaneous CSRs 87.9000.0000 – 87.9FFF.FFFF 0.25 21174 power management CSRs 87.A000.0000 –...

  • Page 72: Address Map

    Address Map The 21164 address space is divided into two regions using physical address <39>: • 0 – 21164 access is to the cached memory space. • 1 – 21164 access is to noncached space. This noncached space is used to access memory-mapped I/O devices.

  • Page 73: Address Space Overview

    Address Map Figure A–1 Address Space Overview 21164 Environment Main System Memory PCI Window Memory Space 21164 Device Device PCI I/O Space Configuration CSRs Space DMA access to the system memory is achieved using windows in one of the follow- ing three ways: •...

  • Page 74: Pci Address Space

    PCI Address Space Figure A–2 Memory Remapping 21164 CPU Cached Memory Space (8GB) PCI Memory Space Page PCI Window Direct Map PCI Window Scatter-Gather LJ-05396.AI4 A.2 PCI Address Space The system generates 32-bit PCI addresses but accepts both 64-bit address (DAC cycles and 32-bit PCI address (SAC ) cycles.

  • Page 75: 21164 Address Space

    21164 Address Space A.3 21164 Address Space Figure A–3 shows an overview of the 21164 address space. Figure A–4 shows how the 21164 address map translates to the PCI address space and how PCI devices access the 21164 memory space using DMA transactions. The PCI memory space is double mapped via dense and sparse space.
  • Page 76 21164 Address Space Figure A–3 21164 Address Space Configuration 21164 Memory Space Scatter-Gather Cached Memory Direct Translation PCI Windows Reserved PCI Memory Space PCI Memory Dense Space PCI I/O Space PCI Memory Sparse Space PCI I/O 21164 Programmed I/O Space DMA Read/Write LJ-05397.AI4 System Address Space...
  • Page 77 21164 Address Space Figure A–4 21164 and DMA Read and Write Transactions Physical Size Address 000XX 00.0000.0000 8GB Cached Memory 01.FFFF.FFFF 02.0000.0000 Reserved 0=Cached Memory Space 7F.FFFF.FFFF 00XXX 80.0000.0000 PCI Memory 83.FFFF.FFFF Sparse Space 0100X 84.0000.0000 704MB Maximum 84.FFFF.FFFF 01010 85.0000.0000 1=Noncached 01011...

  • Page 78: System Address Map

    21164 Address Space A.3.1 System Address Map Figure A–5 shows the following system address regions: • Main memory address space contains 8GB. All transactions contain 64 bytes, are cache-block aligned, and are placed in cache by the 21164. Both Istream and Dstream transactions access this address space.

  • Page 79: System Address Map

    21164 Address Space Figure A–5 System Address Map Main Memory — 8GB 34 33 Memory Address PCI Sparse Memory Space — 512MB Region 1 34 33 PCI Memory Address <28:2> Size PCI Sparse Memory Space — 128MB Region 2 34 33 32 2 1 0 PCI Memory Address <26:2>...

  • Page 80: 21164 Byte/Word Pci Space

    21164 Byte/Word PCI Space Figure A–6 21174 CSR Space PCI Configuration Space 34 33 32 28 27 2 1 0 Address Size Space CPU Address Size (GB) Contents PCI Configuration Space PCI IACK/Special Cycle 0.25 21174 Main CSRs 0.25 Main Memory Control CSRs 0.25 21174 Address Translation 0.25...

  • Page 81: Byte/Word Pci Space

    21164 Byte/Word PCI Space Figure A–7 Byte/Word PCI Space PCI Memory Space — 4GB 35 34 33 32 2 1 0 1 Size PCI Memory Address <31:2> PCI I/O Space — 4GB 35 34 33 32 1 Size PCI I/O Address PCI Type 0 Configuration Space —...

  • Page 82: 21164 Size Field

    21164 Byte/Word PCI Space Table A–3 shows noncached 21164 addresses when byte/word support is enabled. Table A–3 21164 Byte/Word Addressing int4_valid addr_h Instruction <38:37> <3> <2> <1> <0> INT8 — — — addr_h<3:2> — Undefined — LDWU addr_h<3:1> — — Undefined LDBU addr_h<3:0>...

  • Page 83: Cacheable Memory Space

    Cacheable Memory Space A.5 Cacheable Memory Space Cacheable memory space is located in the range 00.0000.0000 to 01.FFFF.FFFF. The 21174 recognizes the first 8GB to be in cacheable memory space. The block size is fixed at 64 bytes. Read and flush commands to the 21164 caches occur for DMA traffic.
  • Page 84 PCI Dense Memory Space • The concept of dense space (and sparse space) is applicable only to a 21164-gen- erated address. There is no such thing as dense space (or sparse space) for a PCI generated address. • Byte or word transactions are not possible in dense space. The minimum access granularity is a longword on write transactions and a quadword on read transac- tions.

  • Page 85: Pci Sparse Memory Space

    PCI Sparse Memory Space Figure A–8 shows dense-space address generation. Figure A–8 Dense-Space Address Generation 21164 Address 34 33 32 31 05 04 02 01 00 39 38 <31:5> int4_valid 21164 05 04 02 01 00 PCI Dense Memory Address LJ04264A.AI4 The following list describes address generation in dense space: •...

  • Page 86: Hardware Extension Register (Hae_Mem

    PCI Sparse Memory Space A.7.1 Hardware Extension Register (HAE_MEM) In sparse space, addr_h<7:3> are used to encode byte enable bits, size bits and the low-order PCI address, ad<2:0>. This means that there are now five fewer address bits available to generate the PCI physical address. The system provides three sparse-space PCI memory regions and allows all three sparse-space regions to be relocated by way of bits in the HAE_MEM register.

  • Page 87: Int4_Valid And 21164 Address Relationship

    PCI Sparse Memory Space • Hardware does not perform read-ahead (prefetch) transactions in sparse space because read-ahead transactions may have detrimental side effects. • Programmers are required to insert memory barrier (MB) instructions between sparse-space transactions to prevent collapsing in the 21164 write buffer. How- ever, this is not always necessary.

  • Page 88: Pci Memory Sparse-Space Read/Write Encodings

    PCI Sparse Memory Space Table A–6 defines the low-order PCI sparse memory address bits. Signals addr_h<7:3> are used to generate the length of the PCI transaction in bytes, the byte enable bits, and ad<2:0>. The 21164 signals addr_h<30:8> correspond to the quad- word PCI address and are sent out on ad<25:3>.

  • Page 89: Pci Memory Sparse-Space Address Generation - Region

    The high-order ad<31:26> are obtained from either the hardware extension register (HAE_MEM) or the 21164 address depending on sparse-space regions, as shown in Table A–7. See the DIGITAL Semiconductor 21174 Core Logic Chip Technical Ref- erence Manual for more information about the 21174 HAE_MEM CSR.

  • Page 90: Pci Memory Sparse-Space Address Generation - Region

    PCI Sparse Memory Space Figure A–10 shows the mapping for region 2. Figure A–10 PCI Memory Sparse-Space Address Generation – Region 2 21164 Address 34 33 32 31 05 04 03 02 39 38 PCI QW Address int4_valid 21164 HAE_MEM CSR Length in Bytes Byte Offset 27 26...

  • Page 91: Pci Sparse I/O Space

    PCI Sparse I/O Space A.8 PCI Sparse I/O Space The PCI sparse I/O space is divided into two regions — region A and region B. Region A addresses the lower 32MB of PCI I/O space and is never relocated. This region will be used to address the (E)ISA devices.

  • Page 92: Pci Sparse I/O Space Read/Write Encodings

    PCI Sparse I/O Space Table A–8 contains the PCI sparse I/O space read/write encodings. Table A–8 PCI Sparse I/O Space Read/Write Encodings Size Byte Offset 21164 Data-In Register addr_h Instruction PCI Byte Byte Lanes addr_h<4:3> <6:5> Allowed ad<2:0> Enable 63..32 31..0 A<7>...

  • Page 93: Pci Sparse I/O Space Address Translation (Region A, Lower 32Mb)

    PCI Sparse I/O Space Figure A–12 PCI Sparse I/O Space Address Translation (Region A, Lower 32MB) 21164 Address 39 38 34 33 32 31 30 29 05 04 03 02 0 1 1 0 int4_valid 21164 Length in Bytes Byte Offset 25 24 02 01 00 0 0 0 0 0 0 0...

  • Page 94: Pci Configuration Space

    PCI Configuration Space A.9 PCI Configuration Space The PCI configuration space is located in the range 87.0000.0000 to 87.1FFF.FFFF. Software is advised to clear PYXIS_CTRL<FILL_ERR_EN> when probing for PCI devices by way of configuration space read transactions. This will prevent the 21174 from generating an ECC error if no device responds to the configuration cycle (and random data is picked up on the PCI bus).

  • Page 95: Pci Configuration Space Definition (Sparse)

    PCI Configuration Space Figure A–14 PCI Configuration Space Definition (Sparse) CPU Address 29 28 21 20 16 15 13 12 07 06 05 04 03 02 Length Byte Offset CFG<1:0> 11 10 02 01 00 Type 0 PCI Configuration IDSEL Function Register Address...

  • Page 96: Cpu Address To Idsel Conversion

    PCI Configuration Space Peripherals are selected during a PCI configuration cycle if the following three con- ditions are met: 1. Their IDSEL pin is asserted. 2. The PCI bus command indicates a configuration read or write. 3. Address bits <1:0> are 00. Address bits <7:2>...

  • Page 97: Pci Configuration Space Read/Write Encodings

    PCI Configuration Space If a quadword access is specified for the configuration cycle, then the Note: least significant bit of the register number field (such as ad<2>) must be zero. Quadword transactions must access quadword aligned registers. If the PCI cycle is a configuration read or write cycle but the ad<1:0> are 01 (that is, a type 1 transfer), then a device on a hierarchical bus is being selected via a PCI-to- PCI bridge.

  • Page 98: Pci Bus Hierarchy

    PCI Configuration Space archically behind it. If the bus number of the configuration cycle matches the bus num- ber of the bridge chip’s secondary PCI interface, it will accept the configuration cycle, decode it, and generate a PCI configuration cycle with ad<1:0> = 00 on its secondary PCI interface.

  • Page 99: Pci Special/Interrupt Cycles

    PCI Special/Interrupt Cycles A.10 PCI Special/Interrupt Cycles PCI special/interrupt cycles are located in the range 87.2000.0000 to 87.3FFF.FFFF. The Special cycle command provides a simple message broadcasting mechanism on the PCI. The Intel processor uses this cycle to broadcast processor status; but in gen- eral it may be used for logical sideband signaling between PCI agents.

  • Page 100: Pci To Physical Memory Address

    CSRs, addr_h<27:6> specifies a longword address where addr_h<5:0> must be zero. All the 21174 registers are accessed with a LW granularity. For more specific details on the 21174 CSRs, see the DIGITAL Semiconductor 21174 Core Logic Chip Technical Reference Manual. For the flash ROM, addr_h<30:6> defines a byte address.

  • Page 101: Pci Target Window Mask Register Fields

    PCI to Physical Memory Address Table A–12 shows the PCI target window mask fields. Table A–12 PCI Target Window Mask Register Fields PCI_MASK<31:20> Size of Window Value of n 0000 0000 0000 0000 0000 0001 0000 0000 0011 0000 0000 0111 0000 0000 1111 16MB 0000 0001 1111...
  • Page 102 PCI to Physical Memory Address The window base address must be on a naturally aligned boundary address depend- ing on the size of the window . This rule is not particularly difficult to obey, because the address space of any PCI device can be located anywhere in the PCI’s 4GB memory space, and this scheme is compatible with the PCI specification: A PCI device specifies the amount of memory space it requires via the Base reg- isters in its configuration space.

  • Page 103: Pci Dma Addressing Example

    PCI to Physical Memory Address Figure A–17 PCI DMA Addressing Example 21164 System PCI Device's DMA Memory Space Page Scatter-Gather PCI Memory Device 0 Device 1 Device 2 Space (4GB) 21164 Memory Space (8GB) LJ-05402.AI4 Figure A–18 shows the PCI window logic. The comparison logic associated with ad<63:32>...

  • Page 104: Pci Target Window Compare

    PCI to Physical Memory Address Figure A–18 PCI Target Window Compare PCI Address n n-1 20 19 Target Hit (Window 3 Only) Compare & Zero Hit Window 3 Window Hit Logic Detect Hit Window 2 Hit Logic Hit Window 1 Hit Window 0 W_DAC Window Enable (WENB)

  • Page 105: Direct-Mapped Addressing

    Direct-Mapped Addressing A.13 Direct-Mapped Addressing The target address is translated by direct mapping or scatter-gather mapping as deter- mined by the Wx_BASE_SG (scatter-gather) bit of the window’s PCI base register. If the Wx_BASE_SG bit is clear, the DMA address is direct mapped, and the trans- lated address is generated by concatenating bits from the matching window’s trans- lated base register (T_BASE) with bits from the incoming PCI address.

  • Page 106: Scatter-Gather Addressing

    Scatter-Gather Addressing Table A–13 Direct-Mapped PCI Target Address Translation (Sheet 2 of 2) W_MASK<31:20> Size of Window Translated Address <32:2> 0111 1111 1111 Translated Base<33:31> : ad<30:2> 1111 1111 1111 Translated Base<33:32> : ad<31:2> Otherwise Not supported — A.14 Scatter-Gather Addressing If the Wx_BASE_SG bit of the PCI base register is set, then the translated address is generated by a lookup table.

  • Page 107: Scatter-Gather Pte Format

    Scatter-Gather Addressing Each scatter-gather map page table entry (PTE) is a quadword and has a valid bit in bit position 0, as shown in Figure A–19. Address bit 13 is at bit position 1 of the map entry. Because the 21174 implements valid memory addresses up to 16GB, then bits <63:22>...

  • Page 108: Scatter-Gather Tlb

    Scatter-Gather TLB Table A–14 Scatter-Gather Mapped PCI Target Address Translation (Sheet 2 of 2) Size of SG W_MASK<31:20> Map Table Translated Address <32:2> 0000 0001 1111 32KB Translated Base<33:15> : ad<24:13> 0000 0011 1111 64KB Translated Base<33:16> : ad<25:13> 0000 0111 1111 128KB Translated Base<33:17>...

  • Page 109: Scatter-Gather Associative Tlb

    Scatter-Gather TLB Figure A–20 Scatter-Gather Associative TLB Address 8KB CPU Page Address Cycle <31:15> D A T A PCI Address<14:13> Memory Page Address<32:13> Address<12:2> Physical Memory Index Dword Address LJ04276A.AI4 Each time an incoming PCI address hits in a PCI target window that has scatter- gather translation enabled, ad<31:15>...

  • Page 110: Scatter-Gather Tlb Hit Process

    Scatter-Gather TLB mapping. Both paths are indicated — the right side shows the path for a TLB hit, while the left side shows the path for a TLB miss. The scatter-gather TLB is shown in a slightly simplified, but functionally equivalent form. A.15.1 Scatter-Gather TLB Hit Process The process for a scatter-gather TLB hit is as follows: 1.

  • Page 111: Scatter-Gather Map Translation

    Scatter-Gather TLB Figure A–21 Scatter-Gather Map Translation 40 39 32 31 20 19 0000000000000000000 Offset Window Compare Logic ad_h<31:13> sent to TLB for PCI window W_DAC XXXXX Wn_BASE "hit." DAC indicator 11111 Wn_MASK 00000000 also sent. n-11 n-10 000000000 Tn_BASE Tn_BASE Select n-10 n-11...

  • Page 112: Default Pci Window Allocation

    Suggested Use of a PCI Window A.16 Suggested Use of a PCI Window Figure A–22 shows the PCI window assignment after power is turned on (configured by firmware), and Table A–15 lists the details. PCI window 0 was chosen for the 8MB to 16MB EISA region because this window incorporates the mem_cs_l logic.

  • Page 113: Suggested Use Of A Pci Window

    Suggested Use of a PCI Window Table A–15 lists the PCI window power-up configuration characteristics. Table A–15 PCI Window Power-Up Configuration PCI Window Assignment Size Comments Scatter-gather Not used by firmware; mem_cs_l disabled Direct-mapped Mapped to 0GB to 1GB of main memory Disabled —...
  • Page 114 Suggested Use of a PCI Window This mem_cs_l range in Figure A–23 is subdivided into several portions (such as the BIOS areas) that are individually enabled/disabled using CSRs as listed here: • The MCSTOM (top of memory) register has a 2MB granularity and can be pro- grammed to select the regions from lMB up to 512MB.
  • Page 115 Suggested Use of a PCI Window As shown in Figure A–24, PCI window 0 in the 21174 can be enabled to accept the mem_cs_l signal as the PCI memory decode signal. With this path enabled, the PCI window hit logic simply uses the mem_cs_l signal. For example, if mem_cs_l is asserted, then a PCI window 0 hit occurs and the devsel signal is asserted on the PCI.

  • Page 117: Supporting Products

    Supporting Products This appendix lists sources for components and accessories that are not included with the AlphaPC 164LX. For the latest information, visit the Alpha website at URL: http://www.alpha.digital.com. Click on Motherboard Products. The hardware compatibility list (HCL) and the qualified-memory vendor list are also available at this location.
  • Page 118 Memory Kingston Technology Company 17600 Newhope Street Fountain Valley, CA 92708 Phone: 1-800-845-2545 Micron Semiconductor Products, Inc. 8000 South Federal Way Mail Stop 607 Boise, ID 83706 Phone: 208-368-3900 Fax: 208-368-5018 NEC Electronics, Inc. The Meadows Building, 4th Floor 161 Worcester Road Framingham, MA 01701 Phone: 508-935-2000 Fax: 508-935-2233...

  • Page 119: Thermal Products

    2859 Bayview Drive Fremont, CA 94538 Phone: 510-770-1200, ext. 312 PN PP-253V (250 W) B.4 Enclosure An enclosure, suitable for housing the AlphaPC 164LX and its power supply, is available from: Axxion Group Corporation 7801 Trade Center Avenue El Paso, TX 79912...
  • Page 121 Support, Products, and Documentation If you need technical support, a DIGITAL Semiconductor Product Catalog, or help deciding which documentation best meets your needs, visit the DIGITAL Semiconductor World Wide Web Internet site: http://www.digital.com/semiconductor You can also contact the DIGITAL Semiconductor Information Line or the DIGITAL Semiconductor Customer Technology Center for support.
  • Page 122 DIGITAL Semiconductor Products To order the AlphaPC 164LX motherboard, contact your local distributor. The fol- lowing tables list some of the semiconductor products available from DIGITAL Semiconductor. Note: The following products and order numbers might have been revised. For the latest versions, contact your local distributor.
  • Page 123 DIGITAL Semiconductor Documentation The following table lists some of the available DIGITAL Semiconductor documenta- tion. Title Order Number Alpha AXP Architecture Reference Manual EY–T132E–DP Alpha Architecture Handbook EC–QD2KB–TE DIGITAL Semiconductor 21164 Alpha Microprocessor EC-QP99B-TE Hardware Reference Manual DIGITAL Semiconductor 21164 Alpha Microprocessor...
  • Page 125 Index Numerics 21164 microprocessor. See Microprocessor. CAS, 4–5 21174 Core logic chip. See Core logic chip. Clocks, 1–4 14.3-MHz reference, 4–8 21174-CA. See Core logic chip. time-of-year, 4–8 37C935. See Combination controller. Combination controller, 1–4, 4–7 82378ZB. See SIO. Communication ports, 4–7 Component list, 2–3 Components and features, 1–1 Abbreviations, x...
  • Page 126 Debug monitor system support, 1–5 bus, 4–5 devices, 4–7 Design support, 1–6 expansion slots, 4–7 DIGITAL UNIX interface, 1–4 SDK support, 1–6 SRM console firmware, 1–5 Dimensions motherboard, 3–2 Jumper configurations, 2–4 Direct mapping, 4–4 Jumper descriptions, 2–3 Diskette controller, 4–7 Jumpers Bcache size, 2–5...
  • Page 127 Motherboard Power supply ATX hole specification, 3–3 dc ampere requirements, 3–1 ATX I/O shield, 3–4 wattage requirements, 3–1 component descriptions, 2–3 Processor. See Microprocessor. configuration jumpers, 2–4 PTE, 4–4 dimensions, 3–2 layout, 2–2 Mouse controller, 4–8 Ranges and extents, xii RAS, 4–5 Reset, 4–17 Numbering convention, xii...
  • Page 128 TLB, 4–4 UARTs, 4–7 Ubus, 4–7, 4–9 UNDEFINED definition, xiii UNIX. See DIGITAL UNIX. UNPREDICTABLE definition, xiii Upgrading memory, 5–2 microprocessor, 5–2 Utility bus. See Ubus. Wave pipelining, 4–2 Windows NT AlphaBIOS firmware, 1–5 SDK support, 1–6 definition, xi 22 January 1998 – Subject to Change...

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