DEC Digital Alpha VME 4/224 Manuals

Manuals and User Guides for DEC Digital Alpha VME 4/224. We have 1 DEC Digital Alpha VME 4/224 manual available for free PDF download: User Manual

DEC Digital Alpha VME 4/224 User Manual

DEC Digital Alpha VME 4/224 User Manual (442 pages)

Brand: DEC | Category: Motherboard | Size: 1.36 MB

Table of Contents

Table of Contents
3
Intended Audience
21
Preface

21
- Purpose of this Manual
  21
1 Product Overview

29
2 Installation Procedures

35
3 Operating the Digital Alpha VME 4 Computer

71
- Controls and Indicators
  71
- Controls and Indicators
  72
- Console Mode
  73
- Entering Console Mode
  73
- Exiting Console Mode
  73
- Environment Variables
  73
- Environment Variable Summary
  74
  - Booting an Operating System
    77
  - Updating Firmware
    77
4 Diagnostics

79
- Overview
  79
- Operating Environments
  79
- POST Diagnostics
  79
- Console Prompt Diagnostics
  80
- Diagnostic Test Descriptions
  80
- Available Console Diagnostics
  80
- Console Diagnostic Tests
  81
  - SROM Initialization Countdown
    82
  - Console POST Descriptions
    83
    
    POST Non-Volatile RAM Diagnostic
    84
    
    POST Memory Diagnostic
    85
  - Console Diagnostic Test Descriptions
    86
    
    Heartbeat Timer Test
    87
    
    Interval Timer Tests
    88
- Loopback Descriptions for Interval Timer Test 3 and
  93
- LAN Address ROM Format
  101
  - NCR 53C810 PCI-SCSI I/O Processor Tests
    102
  - Watchdog Timer Interrupt Test
    105
  - VME Interface Tests
    106
  - Initialization Sequence
    108
- SROM Test Flows
  108
- Console POST Flows
  109
- Console POST Flows
  110
5 System Address Mapping

111
6 Cache and Memory Subsystem

133
- Address and Data Paths of Cache and Memory
  134
  - CA Block Diagram
    135
  - System Bus Interface
    136
  - Arbitration on the System Bus
    136
  - System Bus Controller
    136
  - Decoding Addresses
    136
  - Bcache Control
    137
  - Memory Controller
    137
- Cache Subsystem for a 2 MB Cache
  137
  - Memory Organization
    138
- Maximum and Minimum DIMM Bank Layouts
  138
  - Memory Address Generation
    139
  - Support for Memory
    139
  - Minimizing Read Latency
    139
  - Transaction Scheduler
    139
  - Programmable Memory Timing
    139
  - Presence Detect Logic
    140
  - Error Handling
    140
  - Address Space of Control/Status Registers
    140
- CSR Register Addresses for Decchip 21071-CA
  141
- Error and Diagnostic Status Register
  141
  - Description of Csrs
    143
  - General Control Register
    143
- General Control Register: 0X180000000
  143
  - Error and Diagnostic Status Register
    145
- Error and Diagnostic Status Register: 0X180000020
  146
  - Tag Enable Register
    148
- Tag Enable Register: 0X180000060
  148
- Cache Size Tag Enable Values
  149
  - Error Low Address Register
    150
- Maximum Memory Tag Enable Values
  150
  - Error High Address Register
    151
  - Ldx_L Low Address Register
    151
- Error Low Address Register: 0X180000080
  151
- Error High Address Register: 0X1800000A0
  151
  - Ldx_L High Address Register
    152
  - Memory Control Registers
    152
    
    Presence Detect Low-Data Register
    152
    
    Presence Detect High-Data Register
    153
    
    Base Address Registers
    153
- Presence Detect Low-Data Register: 0X180000280
  153
- Presence Detect High-Data Register: 0X180000260
  153
  - Conﬁguration Registers
    154
- Bank 0 Base Address Register: 0X180000800
  154
- Conﬁguration Registers for Bank Set 0: 0X180000A00
  154
  - Conﬁguration Register for Banks 0 and 1 . . . . . . . . . . 6-7 Timing Register a
    155
    
    Bank Set Timing Registers
    156
- Bank Set 0 Timing Register A: 0X180000C00
  157
- Bank Set 0 Timing Register B: 0X180000E00
  158
- Timing Register B
  158
  - Global Timing Register
    159
  - Refresh Timing Register
    160
- Global Timing Register: 0X180000200
  160
- Refresh Timing Register: 0X180000220
  161
  - Data Path
    162
- Block Diagram of the Decchip 21071-BA
  162
  - Memory Read Buffer
    163
  - I/O Read Buffer and Merge Buffer
    163
  - I/O Write and DMA Read Buffer
    163
  - DMA Write Buffer
    163
  - Memory Write Buffer
    164
  - Error Handling
    164
7 PCI Host Bridge

165
- Interface to the System Bus
  166
- Decoding Physical Addresses
  166
- Decchip 21071-DA Block Diagram
  166
  - Buffering System Bus Transactions
    167
  - Burst Length and Prefetching for the System Bus
    167
  - Interface to the PCI Bus
    167
  - Decoding PCI Addresses
    167
  - Buffering PCI Transactions
    167
  - Burst Length and Prefetching for PCI Bus
    168
  - Features
    168
  - Burst Order
    168
  - Parity Support
    168
  - Data Coherency
    169
  - Interrupts
    170
    
    Exclusive Access
    170
  - Bus Parking
    170
  - Retry Timeout
    171
  - PCI Master Timeout
    171
  - Address Stepping in Conﬁguration Cycles
    171
  - Address Space of Control/Status Registers
    171
- Decchip 21071-DA CSR Addresses
  171
- Host Address Extension Register 1
  172
- Host Address Extension Register 2
  172
  - Description of Csrs
    173
  - Diagnostic Control/Status Register
    173
- Diagnostic Control/Status Register: 0X1A0000000
  174
  - PCI Error Address Register
    177
  - System Bus Error Address Register
    178
- PCI Error Address Register: 0X1A0000020
  178
- System Bus Error Address Register: 0X1A0000040
  178
  - Dummy Registers 1 through 3
    179
  - Translated Base Registers 1 and 2
    179
- Translated Base Registers 1, 2: 0X1A00000C0, 0X1A00000E0
  179
  - PCI Base Registers 1 and 2
    180
- PCI Base Registers 1 and 2: 0X1A0000100, 0X1A0000120
  180
  - Translated Base Registers 1 and 2 . . . . . . . . . . . . . . . . 7-6 PCI Base Registers 1 and 2
    180
  - PCI Mask Registers 1 and 2
    181
- PCI Mask Registers 1 and 2: 0X1A0000140, 0X1A0000160
  181
  - Host Address Extension Register 1
    182
  - Host Address Extension Register 2
    182
- Host Address Extension Register 0: 0X1A0000180
  182
- Host Address Extension Register 1: 0X1A00001A0
  182
- Host Address Extension Register 2: 0X1A00001C0
  183
  - PCI Master Latency Timer Register
    184
  - TLB Tag Registers 0 through 7
    184
- PCI Master Latency Timer Register: 0X1A00001E0
  184
  - TLB Data Registers 0 through 7
    185
- TLB Tag Registers 0 through 7: 0X1A0000200 to 0X1A00002E0
  185
- TLB Data Registers 0 through 7: 0X1A0000300 to 0X1A00003E0
  185
  - TLB Tag Registers 0 through
    185
  - Translation Buffer Invalidate All Register: 0X1A0000400
    186
- TLB Data Registers 0 through 7
  186
8 PCI Bus

187
- PCI Bus and Interfaces to the I/O Subsystem
  188
  - Ethernet Controller
    189
  - PCI Conﬁguration Registers
    189
  - Ethernet Controller Csrs
    190
  - PCI Cycles
    191
- Ethernet Controller Csrs
  191
  - Ethernet Address
    192
  - SCSI Controller
    192
  - Connection and Termination
    192
- Decchip 21040-AA CSR9 (ENET ROM Register)
  192
  - Scsi ID
    193
  - Programming
    193
  - PCI Conﬁguration Registers
    193
  - SCSI Control Status Registers
    194
- PCI Conﬁguration Block
  194
- SCSI Controller Csrs
  195
  - PCI I/O Companion Card
    197
9 Nbus

199
- Nbus Address Space
  199
- Nbus and Nbus Resources
  199
  - SIO Chip PCI Conﬁguration Space
    200
- PCI Control Register
  200
  - PCI Control Register
    201
- SIO Conﬁguration Block
  201
  - ISA Controller Recovery Timer Register
    202
  - ISA Clock Divisor Register
    202
  - Module Registers
    202
  - Module Display Control Register
    203
  - Module Conﬁguration Register
    204
- Module Display Control Register
  204
- DIMM Identiﬁcation
  207
- Memory Identiﬁcation Register
  208
- Presence Detect
  209
  - Reset Reason Registers
    210
- ID Bits
  210
- Memory DIMM Conﬁguration Bit
  210
  - Reset Reason Registers
    211
  - Heartbeat Register
    212
  - Module Control Register 1
    212
  - Module Control Register
    213
  - Bcache Conﬁguration Register
    214
  - Rom
    215
- Bcache Size and Speed Decode
  215
  - Super I/O Chip
    216
  - Serial Port Channels a and B
    216
- Flash ROM Layout/Addressing
  216
  - Super I/O Register Address Space
    217
- Super I/O Register Address Space Map
  217
  - Keyboard and Mouse Controller
    219
- Integrated Device Electronics Register Addresses
  219
  - TOY Clock
    220
- Keyboard and Mouse Controller Addresses
  220
  - TOY Clock Timekeeping Registers
    221
  - TOY Clock Command Register
    222
  - Interval Timing Registers
    223
- 82C54 Control Byte
  224
- Timer Interface Registers
  224
  - Interval Timing Control Register
    224
  - Interval Timing Control Register
    225
  - Timer Registers
    226
- 82C54 Timer Data Access
  226
  - Timer Modes
    227
  - Interrupts
    229
- Timer Clocking
  229
  - Timer Interrupt Status Registers
    230
- Timer Interrupt Status Register
  230
  - Watchdog Timer
    231
- Watchdog Timer Registers
  232
- Watchdog Timer TOY Clock Command Register
  232
- Watchdog Timer Module Control Register
  233
- Watchdog Timer TOY Clock Command Register
  233
  - Nonvolatile RAM
    234
- NVRAM Access
  234
10 VME Interface

235
- VME Interface Block Diagram
  235
  - Vmebus Master
    236
- Mapping Window_1 and Window_2
  237
  - Outbound Scatter-Gather Mapping
    238
- Mapping Pages from PCI to VME
  238
- Outbound Scatter-Gather Entry
  239
  - Address Modiﬁer
    240
  - Read-Modify-Write
    240
- Formation of Address Modiﬁer Codes from Scatter-Gather Entry
  240
  - Data Transfers
    241
    
    Single Mode Transfers
    241
    
    Block Mode Transfers
    241
- VIC Block Transfer Control Register
  242
  - Requesting the Vmebus
    243
  - Vmebus Slave
    243
  - Decoding Addresses
    244
- Mapping Pages of Memory from Vmebus to PCI Bus
  244
- Address Decoding
  245
- Base and Mask Register
  245
  - Inbound Scatter-Gather Entries
    246
- Inbound Scatter-Gather Entry with A32 Address Mapping
  246
- VME Address
  246
- VME Interface Processor Page Monitor CSR
  247
- PCI Address
  247
  - Interprocessor Communication
    248
    
    Interprocessor Communication Registers
    248
    
    Interprocessor Communication Global Switches
    248
- VME Interface Processor Page Monitor CSR
  248
  - Interprocessor Communication Module Switches
    249
- Interprocessor Communication Register Map through
  249
  - System Controller Operation
    251
  - Arbitrating the Vmebus
    252
    
    Requesting the Vmebus
    252
- VIC Arbiter/Requester Conﬁguration Register
  252
  - Releasing the Vmebus
    253
- Arbiter/Requester Conﬁguration Register
  253
- VIC Release Control Register
  254
  - System Clock Output
    255
  - Timeout Timers
    255
    
    Arbitration Timers
    255
    
    Vmebus Transfer Timers
    256
- Vmebus Transfer Timeout Register
  256
  - Local Bus Transfer Timer
    257
  - Vmebus Interrupt Handling
    257
- VIC Interrupt Request/Status Register
  258
- Vmebus Interrupt Vector Base Registers
  259
- Vmebus Interrupter Interrupt Control Register
  259
  - Byte Swapping
    260
  - DC7407 Byte Swapping
    260
  - VIC64 Byte Swapping
    261
- Swap Modes
  262
- Big Endian VME Byte Lane Formats
  262
- PCI BE# to Local A1,0 and SIZ1,0 Translation for Various Swap Modes
  263
  - Initializing the VME Interface
    264
  - VME PCI Conﬁguration Registers
    264
- Local Bus A1,0 and SIZ1,0 to PCI BE# Translation
  264
  - Programming Scatter-Gather RAM
    265
- Access to PCI Memory Addresses
  265
11 System Interrupts

275
- Table of CPU Interrupt Assignments
  275
- Block Diagram of the Interrupt Logic
  276
  - Xilinx Interrupt Controller
    276
- Interrupt/Mask Register #1
  277
- Interrupt/Mask Register #2
  277
  - VIC64 Chip System Interrupt Controller
    278
- Interrupt/Mask Register #3
  278
- Interrupt/Mask Register #4
  278
  - Basic Operation
    279
- Generic ICR
  279
  - VIC64 Chip Interrupt Sources
    280
    
    Local Device Interrupts
    280
- VIC64 Chip Interrupt Ranking
  280
  - Vmebus Interrupt Requests
    281
- Device Icrs
  281
- VIC Local Interrupt Vector Base Register
  281
  - Status/Error Interrupts
    282
- VME IRQ* Icrs
  282
- VME IRQ ICR Priority Assignments
  282
- DMA Status ICR
  283
- VIC Error Group ICR
  284
- Vmebus Interrupter ICR
  284
  - SIO Chip Programmable Interrupt Controller
    285
    
    Nonmaskable System Events
    285
- VIC Error Group Interrupt Vector Base Register
  285
  - NMI Status and Control Register
    286
- NMI Status and Control Register Bits
  286
  - EPIC Interrupt
    287
  - Module Reset
    287
12 Console Primer

289
- About the Console
  289
- Console Features
  289
- Command Overview
  290
- Commonly Used Commands
  290
  - Shell Operators
    291
- Console Shell Operators
  291
  - Using Flow Control
    292
  - Getting Information about the System
    293
  - Getting Help
    294
  - Examining and Depositing to Memory or System Registers
    295
  - Accessing Memory
    297
  - Examining Registers
    298
  - Using Pipes and Grep to Filter Output
    300
  - Using I/O Redirection (>)
    300
  - Running Commands in Background
    301
  - Monitoring Status
    301
  - Killing a Process
    302
  - Creating Scripts
    302
  - Copying Scripts over the Network
    303
- Digital Alpha VME 4 Console Command Summary
  306
13 Console Commands

309
- Special Keys
  309
- Command Line Characteristics
  310
- Radix Control
  310
- Console Command Dictionary
  311
  - Alloc
    312
  - Boot
    314
  - Break
    322
  - Cat
    323
  - Chmod
    324
  - Chown
    326
  - Clear
    327
  - Clear_Log
    328
  - Date
    329
- Echo
  338
- Eval
  340
  - Deposit
    347
- Examine
  347
- Exer
  348
- Exit
  357
- False
  358
- Free
  359
- Grep
  360
- Help
  365
- Init_Ev
  367
- Initialize
  368
- Kill
  369
- Line
  370
- Memexer
  372
- Memtest
  372
- Net
  380
- Pwrup
  384
- Semaphore
  387
- Set
  388
- Set Led
  391
- Set Reboot Srom
  392
- Set Toy Sleep
  393
- Show
  396
- Show Conﬁg
  398
- Show Device
  399
- Show Hwrpb
  401
- Show Led
  402
- Show Map
  403
- Show_Log
  404
- Sleep
  406
- Sort
  407
  - Start
    409
  - Stop
    410
  - Update
    411
A Module Connector Pinouts

415
Index

425

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