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Figure 10–18 Big Endian VME Byte Lane Formats
A31
byte 0
byte 1
byte 2
The longword transfers, tribyte transfers, and unaligned word transfers all use
the byte lanes in the same way. However, when the low word in a longword is
transferred, the data is switched to or from its usual lanes D<31:16> to or from
D<15:0>. Byte transfers in the low word of a longword are swapped in a similar
way.
The single data transfers, D64, are a special case. The VIC64 chip packs the data
to form quadwords in the CY7C964s and on the VMEbus. Only full quadword
block mode transfers are allowed in D64 mode.
Table 10–13 shows the local bus address and size signals used for the DC7407's
swap modes when the DC7407 is master of the local bus. When consulting the
table, keep the following in mind:
•
Cycles in which data moves to or from the D0-16 lane are marked with ''L''.
•
Cycles that would cause a noncontiguous arrangement of bytes on the
VMEbus are not allowed and are aborted on the PCI bus.
•
No cycles are generated for PCI transfers with noncontiguous PCI byte
enables, but these cycles are included in the table for completeness.
10–28 VME Interface
A0
D31
byte 3
byte 4
byte 5
byte 0
byte 1
byte 1
byte 0
byte 1
byte 1
D0
byte 6
byte 7
byte 2
byte 3
byte 2
byte 3
byte 2
byte 2
byte 0
byte 1
byte 2
byte 3
byte 0
byte 1
byte 2
byte 3
ML013371
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Troubleshooting
