DEC Digital Alpha VME 4/224 User Manual page 268

Bits 7-2 User defined. Combines with ICMS switch number to provide vector.
LIVBR
Bits 1-0 Read only.
Bits 7-2 User defined. Combines with LIRQ number to provide vector.
EGIVBR
Bits 1-0 Read only.
Bits 7-2 User defined. Combines with fixed codes to provide vector.
ICFSR
Bits 3-0 Module switches.
Bits 7-4 Global switches.
ICR0-4 General-purpose registers. Accessible over the VMEbus or local bus.
ICR5 Read-only register containing the VIC64 revision. Accessible over
VMEbus or local bus.
ICR6
Bits 1-0 Read only from the VMEbus. Must be cleared by the processor after
reset.
Bits 5-2 Reserved, must read as 1s.
Bit 6 Must be cleared by the processor after reset. If enabled by LICR7, this
bit being set asserts SYSFAIL* on the VMEbus.
Bit 7 Read only.
ICR7
Bits 4-0 Read and write from the VMEbus or local bus. These bits are set if the
corresponding ICR is written.
Bit 5 Read only.
Bit 6 HALT and RESET control.
Bit 7 VME SYSFAIL* mask, must be set after reset if resets are not to be
translated into SYSFAIL* assertion.
VIRSR
Bit 0 Enable VMEbus interrupter.
Bits 7-1 If bit 0 is set during the write that sets a bit, the corresponding
VMEbus interrupt is asserted. These bits are cleared if bit 0 is cleared
during the write that sets a bit.
VIVBR1-7 Each register sets the vector returned on VMEbus interrupt
acknowledge cycles at that interrupt level.
TTR
10–34 VME Interface