DEC Digital Alpha VME 4/224 User Manual page 144

Table 6–2 General Control Register
Field Name
<15:14> Reserved
<13> BC_BADAP
<12> BC_FRCP
<11> BC_FRCV
<10> BC_FRCD
<9> BC_FRCTAG
<8> BC_IGNTAG
<7> BC_LONGWR
<6> BC_NOALLOC
1
Content of register field after a reset operation.
6–12 Cache and Memory Subsystem
Type Description
MBZ —
1
RW, 0 Bcache force bad address parity. When set,
the tag address parity is loaded as an invalid
address, independent of the value of the BC_
FRCTAG bit.
RW, 0 Bcache force parity. Sets the parity bit on the
next cache fill.
RW, 0 Bcache force valid. Sets the valid bit on the
next cache fill.
RW, 0 Bcache force dirty. Sets the dirty bit on the
next cache fill.
RW, 0 Bcache force tag. When set, the Bcache is
probed for victims, and the line is invalidated
using the values in the BC_FRCD, BC_FRCV,
and BC_FRCP fields. CSRs are used as the
tag controls. Although the line is invalidated
(assuming BC_FRCV is reset), the data is
loaded into the cache, and is returned to the
CPU as cacheable.
Used for diagnostic testing of the cache RAM
and for flushing the cache, clearing BC_FRCV,
and cycling through the address range in the
cache.
RW, 0 Bcache ignore tag. When set, the probes of the
Bcache act as if the valid bit was invalid. All
tag results are ignored and any victims are
lost. Tag and address parity are ignored. This
field can be used to fill the cache with valid
data.
RW, 0 Bcache long write transactions. When set,
write transactions to the cache data RAMs
require two system bus cycles.
RW, 0 Bcache no allocate mode. When set, CPU write
transactions to cacheable memory space are not
allocated into the cache.
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