Pci Configuration Cycles To Primary Bus Targets; Pci Address Decoding For Primary Bus Configuration Accesses - DEC Digital Alpha VME 4/224 User Manual

Table 5–4 PCI Address Decoding for Primary Bus Configuration Accesses
Device Number (sysAdr<20:16>)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101 to 11111
5.1.7.1 PCI Configuration Cycles to Primary Bus Targets
Primary PCI bus devices are selected during a PCI configuration cycle if:
• Their IDSEL# pin is asserted
• The PCI bus command indicates a configuration read or write transaction
• Bits ad<1:0> are 00
Bits ad<7:2>, which are taken from bits sysAdr<12:7>, select a longword register
in the device's 256-byte configuration address space. Configuration accesses
can use byte masks, which may be derived by following the method shown in
Table 5–2.
PCI ad<31:11>
0000 0000 0000 0000 0000 1
0000 0000 0000 0000 0001 0
0000 0000 0000 0000 0010 0
0000 0000 0000 0000 0100 0
0000 0000 0000 0000 1000 0
0000 0000 0000 0001 0000 0
0000 0000 0000 0010 0000 0
0000 0000 0000 0100 0000 0
0000 0000 0000 1000 0000 0
0000 0000 0001 0000 0000 0
0000 0000 0010 0000 0000 0
0000 0000 0100 0000 0000 0
0000 0000 1000 0000 0000 0
0000 0001 0000 0000 0000 0
0000 0010 0000 0000 0000 0
0000 0100 0000 0000 0000 0
0000 1000 0000 0000 0000 0
0001 0000 0000 0000 0000 0
0010 0000 0000 0000 0000 0
0100 0000 0000 0000 0000 0
1000 0000 0000 0000 0000 0
0000 0000 0000 0000 0000 0
System Address Mapping 5–9